Philips PLC42VA12A, PLC42VA12FA, PLC42VA12IA, PLC42VA12IFA, PLC42VA12IN Datasheet
...
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
|
|
|
CMOS programmable multi-function PLD |
PLC42VA12 |
|
(42 × 105 × 12) |
||
|
||
|
|
|
|
|
DESCRIPTION
The new PLC42VA12 CMOS PLD from Philips Semiconductors exhibits a unique combination of the two architectural concepts that revolutionized the PLD marketplace.
The Philips Semiconductors unique Output Macro Cell (OMC) embodies all the advantages and none of the disadvantages associated with the ªVº type Output Macro Cell devices. This new design, combined with added functionality of two programmable arrays, represents a significant advancement in the configurability and efficiency of multi-function PLDs.
The most significant improvement in the Output Macro Cell structure is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other ªVº type devices, the register in the PLC42VA12 Macro Cell remains fully functional as a buried register. Both the combinatorial I/O and buried register have separate input paths (from the AND array). In most V-type architectures, the register is lost as a resource when the cell is configured as a combinatorial I/O. This feature provides the capability to operate the buried register independently from the combinatorial I/O.
The PLC42VA12 is an EPROM-based CMOS device. Designs can be generated using Philips Semiconductors SNAP PLD design software packages or one of several other commercially available JEDEC standard PLD design software packages.
FEATURES
•High-speed EPROM-based CMOS
Multi-Function PLD
±Super set of 22V10, 32VX10 and 20RA10 PAL ICs
•Two fully programmable arrays eliminate ªP-term Depletionº
± Up to 64 P-terms per OR function
•Improved Output Macro Cell Structure
±Individually programmable as:
*Registered Output with feedback
*Registered Input
*Combinatorial I/O with Buried Register
*Dedicated I/O with feedback
*Dedicated Input (combinatorial)
±Bypassed Registers are 100% functional with separate input and feedback paths
±Individual Output Enable control functions
*From pin or AND array
•Reprogrammable ± 100% tested for programmability
•Eleven clock sources
•Register Preload and Diagnostic Test Mode Features
•Security fuse
APPLICATIONS
•Mealy or Moore State Machines
±Synchronous
±Asynchronous
•Multiple, independent State Machines
•10-bit ripple cascade
•Sequence recognition
•Bus Protocol generation
•Industrial control
•A/D Scanning
PIN CONFIGURATIONS
FA and N Pack-
ages
|
|
|
|
|
|
|
|
I0/CLK |
1 |
|
|
|
24 |
VCC |
|
|
|
|
|
|
|
|
|
I1 |
2 |
|
|
|
23 |
M9 |
|
|
|
|
|
|
|
|
|
I2 |
3 |
|
|
|
22 |
M8 |
|
|
|
|
|
|
|
|
|
I3 |
4 |
|
|
|
21 |
M7 |
|
|
|
|
|
|
|
|
|
I4 |
5 |
|
|
|
20 |
M6 |
|
|
|
|
|
|
|
|
|
I5 |
6 |
|
|
|
19 |
M5 |
|
|
|
|
|
|
|
|
|
I6 |
7 |
|
|
|
18 |
M4 |
|
|
|
|
|
|
|
|
|
I7 |
8 |
|
|
|
17 |
M3 |
|
|
|
|
|
|
|
|
|
I8 |
9 |
|
|
|
16 |
M2 |
|
|
|
|
|
|
|
|
|
B0 |
10 |
|
|
|
15 |
M1 |
|
|
|
|
|
|
|
|
|
B1 |
11 |
|
|
|
14 |
M0 |
|
GND |
|
|
|
|
|
|
|
12 |
|
|
|
13 |
I9/OE |
||
|
|
|
|
|
|
|
|
N = Plastic DIP (300mil-wide)
FA = Ceramic DIP with Quartz Window (300mil-wide)
A Package
|
|
|
|
|
|
|
I0/ |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2 |
I1 |
CLK N/C VCC M9 |
M8 |
|
|||||||||||
|
4 |
|
3 |
2 |
|
1 |
|
28 |
|
27 |
|
26 |
|
|
|
|||
I3 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
25 |
M7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
I4 |
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
24 |
M6 |
I5 |
7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
23 |
M5 |
N/C |
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
22 |
N/C |
I6 |
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
21 |
M4 |
I7 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
20 |
M3 |
I8 |
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19 |
M2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12 |
|
13 |
|
14 |
|
15 |
|
16 |
|
17 |
|
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B0 |
B1 GND N/C |
I9/ |
M0 |
M1 |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
OE |
|
|
|
|
|
|
|
A = Plastic Leaded Chip Carrier (450mil-square)
ORDERING INFORMATION
DESCRIPTION |
ORDER CODE |
DRAWING NUMBER |
|
|
|
|
|
24-Pin Ceramic Dual In-Line with window, |
PLC42VA12FA |
1478A |
|
Reprogrammable (300mil-wide) |
|||
|
|
||
|
|
|
|
24-Pin Plastic Dual In-Line, |
PLC42VA12N |
0410D |
|
One Time Programmable (300mil-wide) |
|||
|
|
||
|
|
|
|
28-Pin Plastic Leaded Chip Carrier, |
PLC42VA12A |
0401F |
|
One Time Programmable (450mil-wide) |
|||
|
|
||
|
|
|
PAL is a registered trademark of Advanced Micro Devices, Inc.
October 22, 1993 |
73 |
853±1414 11164 |
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
CMOS programmable multi-function PLD
× × PLC42VA12 (42 105 12)
LOGIC DIAGRAM
|
|
|
|
|
|
|
|
|
|
|
|
R R R R C |
|
|
|
|
|
|
|
|
|
|
|
|
P M MM M K |
|
63 |
56 55 |
48 47 |
40 39 |
32 31 |
24 23 |
16 15 |
8 |
7 |
0 |
FC |
A 8 7 6 5 8 |
I1 |
2 |
|
|
|
|
|
|
|
|
|
|
|
I2 |
3 |
|
|
|
|
|
|
|
|
|
|
|
I3 |
4 |
|
|
|
|
|
|
|
|
|
|
|
I4 |
5 |
|
|
|
|
|
|
|
|
|
|
|
I5 |
6 |
|
|
|
|
|
|
|
|
|
|
|
I6 |
7 |
|
|
|
|
|
|
|
|
|
|
|
I7 |
8 |
|
|
|
|
|
|
|
|
|
|
|
I8 |
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P R |
|
|
|
|
|
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
P R |
|
|
|
|
|
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
P R |
|
|
|
|
|
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
P R |
|
|
|
|
|
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
|
|
|
|
K Q |
NOTE: |
|
|
|
|
|
|
|
|
|
|
|
|
Programmable |
|
|
|
|
|
|
|
|
|
|
|
|
Connection |
|
|
|
|
|
|
|
|
|
|
|
|
October 22, 1993 |
|
|
|
|
74 |
|
|
|
|
|
|
|
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
CMOS programmable multi-function PLD
× × PLC42VA12 (42 105 12)
LOGIC DIAGRAM (Continued)
C C C |
R R R R C C C C |
P R P R C C L L D D D D D D D D |
D D |
|
|
|
||
K K K L |
P M MM M K |
K K K L |
MMM M K |
K M M MM MM M MM M |
M M |
D D |
|
|
7 6 5 A |
B 4 3 2 1 4 |
3 2 1 B |
9 9 0 0 9 |
0 9 0 1 2 3 4 5 6 7 8 |
0 9 |
1 0 |
|
|
|
|
|
|
|
|
13 |
I9/OE |
|
|
|
|
|
|
|
I0/CLK |
|
|
|
|
|
|
|
|
1 |
|
|
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
22 |
M8 |
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
21 |
M7 |
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
20 |
M6 |
|
CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19 |
M5 |
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
18 |
M4 |
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
17 |
M3 |
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
16 |
M2 |
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
15 |
M1 |
|
|
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
23 |
M9 |
|
|
|
P R |
CK |
|
|
|
|
|
|
|
JCK |
|
|
|
|
|
|
|
|
K Q |
|
|
|
|
|
|
|
|
|
|
|
|
14 |
M0 |
|
|
|
|
|
|
|
11 |
B1 |
|
|
|
|
|
|
|
10 |
B0 |
October 22, 1993 |
|
|
|
75 |
|
|
|
|
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
CMOS programmable multi-function PLD
× × PLC42VA12 (42 105 12)
FUNCTIONAL DIAGRAM
P63 |
P0 |
FC |
Ln |
Pn |
Rn |
CKn |
LMn |
PMn |
RMn |
CKn |
DMn |
DMn |
DBn |
|
|
|
|
|
|
|
|
|
|
|
|
|
I9/OE |
I1 ± I8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
I0/CLK |
X1 |
|
|
X2 |
X2 |
X8 |
X8 |
X2 |
X2 |
X2 |
X2 |
X8 |
X2 |
X2 |
|
|
|
|
|
|
|
CLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
CONTROL |
|
|
|
|
|
|
|
|
|
|
P |
R |
|
|
|
|
|
|
|
|
|
|
X8 |
|
J |
CK |
|
|
|
|
|
|
|
|
|
|
|
|
|
X8 |
|
|
|
|
|
|
En (X2) |
|
|
|
X8 |
|
K |
Q |
OMC |
|
|
|
|
OEn |
X8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
CONFIG. |
|
|
|
|
|
|
|
|
|
|
POLARITY |
|
X8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
M1 ± M8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
CONTROL |
|
|
|
|
|
|
|
|
|
|
P |
R |
|
|
|
|
|
|
|
|
|
|
X2 |
|
J |
CK |
|
|
|
|
|
|
|
|
|
|
|
|
X2 |
|
|
|
|
En (X2) |
|
|
|
|
|
|
X2 |
|
K |
Q |
OMC |
OEn |
X2 |
|
|
|
|
|
|
|
|
|
|
|
CONFIG. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
M0, M9 |
|
|
|
|
|
|
|
POLARITY |
X2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
B0 ± B1 |
|
|
|
|
|
|
|
POLARITY |
X2 |
|
|
|
|
|
October 22, 1993 |
|
|
|
|
|
|
76 |
|
|
|
|
|
|
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
CMOS programmable multi-function PLD
× × PLC42VA12 (42 105 12)
ABSOLUTE MAXIMUM RATINGS1
SYMBOL |
PARAMETER |
RATINGS |
UNIT |
|
|
|
|
VCC |
Supply voltage |
±0.5 to +7 |
VDC |
VIN |
Input voltage |
±0.5 to VCC +0.5 |
VDC |
VOUT |
Output voltage |
±0.5 to VCC +0.5 |
VDC |
IIN |
Input currents |
±10 to +10 |
mA |
IOUT |
Output currents |
+24 |
mA |
Tamb |
Operating temperature range |
0 to +75 |
°C |
Tstg |
Storage temperature range |
±65 to +150 |
°C |
NOTE:
1.Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.
THERMAL RATINGS
TEMPERATURE |
|
|
|
Maximum junction |
150°C |
|
|
Maximum ambient |
75°C |
|
|
Allowable thermal |
75°C |
rise ambient to |
|
junction |
|
|
AC TEST CONDITIONS |
VOLTAGE WAVEFORMS |
|
|
|
VCC |
+5V |
S1 |
|
+3.0V |
|
|
90% |
|
|
|
|
|
|
|
|
|
|
|
C1 |
C2 |
|
|
|
|
R1 |
0V |
|
|
10% |
|
|
|
|
OE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
In |
|
MZ |
|
|
5ns |
tR |
tF |
5ns |
|
|
|
|
|
|
|
||||
|
INPUTS |
In |
DUT |
|
R2 |
CL |
+3.0V |
|
|
|
|
|
|
|
|
|
|
90% |
|||
|
|
|
|
|
|
|
|
|
||
|
|
BM |
|
|
|
|
|
|
|
|
|
|
BM |
|
|
|
|
0V |
|
10% |
|
|
|
GND |
MZ |
OUTPUTS |
|
|
|
|
||
|
|
CK |
|
|
5ns |
|
|
5ns |
||
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
MEASUREMENTS: |
|
|
|
NOTE: |
|
|
|
|
|
|
All circuit delays are measured at the +1.5V level |
|||
|
|
|
|
|
|
of inputs and outputs, unless otherwise specified. |
||||
C1 and C2 are to bypass VCC to GND. |
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
||
|
|
Test Load Circuit |
|
|
|
Input Pulses |
|
|||
October 22, 1993 |
77 |
Philips Semiconductors Programmable Logic Devices |
Product specification |
|
|
|
|
CMOS programmable multi-function PLD
× × PLC42VA12 (42 105 12)
DC ELECTRICAL CHARACTERISTICS
0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V
|
|
|
|
|
|
|
|
LIMITS |
|
|
|
|
|
|
|
|
|
|
|
|
|
SYMBOL |
|
|
PARAMETER |
|
TEST CONDITION |
|
MIN |
TYP1 |
MAX |
UNIT |
Input voltage2 |
|
|
|
|
|
|
|
|
||
VIL |
|
Low |
|
|
VCC = MIN |
|
±0.3 |
|
0.8 |
V |
VIH |
|
High |
|
|
VCC = MAX |
|
2.0 |
|
VCC + 0.3 |
V |
Output voltage2 |
|
|
|
|
|
|
|
|
||
VOL |
|
Low |
|
|
VCC = MIN; IOL = 16mA |
|
0.3 |
0.5 |
V |
|
VOH |
|
High |
|
|
VCC = MIN; IOH = ±3.2mA |
2.4 |
4.3 |
|
V |
|
Input current |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
IIL |
|
Low |
|
|
VIN = GND |
|
|
±1 |
±10 |
μA |
IIH |
|
High |
|
|
VIN = VCC |
|
|
+1 |
10 |
μA |
Output current |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
IO(OFF) |
|
Hi-Z state |
|
VOUT = VCC |
|
|
1 |
10 |
μA |
|
|
|
VOUT = GND |
|
|
±1 |
±10 |
μA |
|||
|
|
|
|
|
|
|
||||
I |
|
Short-circuit3,7 |
|
V = GND |
|
|
|
±130 |
mA |
|
OS |
|
|
|
|
OUT |
|
|
|
|
|
I |
|
V |
supply current (Active)4 |
I |
= 0mA, f = 15MHz6, V |
= MAX |
|
90 |
120 |
mA |
CC1 |
|
CC |
|
OUT |
CC |
|
|
|
|
|
I |
|
V |
supply current (Active)5 |
I |
= 0mA, f = 15MHz6, V |
= MAX |
|
70 |
100 |
mA |
CC2 |
|
CC |
|
OUT |
CC |
|
|
|
|
|
Capacitance |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
CI |
|
Input |
|
VCC = 5V; VIN = 2.0V |
|
|
12 |
|
pF |
|
CB |
|
I/O |
|
|
VB = 2.0V |
|
|
15 |
|
pF |
NOTES:
1.All typical values are at VCC = 5V. Tamb = +25°C.
2.All voltage values are with respect to network ground terminal.
3.Duration of short±circuit should not exceed one second. Test one at a time.
4.Tested with VIL = 0.45V, VIH = 2.4V.
5.Tested with VIL = 0V, VIH = VCC.
6.Refer to Figure 1, ICC vs Frequency (worst case). (Referenced from 15MHz)
The ICC increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz. The ICC remains at a worst case for the frequency range of 26MHz up to 37MHz.
The ICC decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz. The worst case ICC is calculated as follows:
±All dedicated inputs are switching.
±All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling.
±All 12 outputs are disabled.
±The number of product terms connected does not impact the ICC.
7. Refer to Figure 2 for tPD vs output capacitance loading.
|
+30 |
|
|
|
|
|
|
|
|
|
+25 |
|
|
|
|
|
|
|
|
|
+20 |
|
|
|
|
|
|
|
|
(mA) |
+15 |
|
|
|
|
|
|
|
|
+10 |
|
|
|
|
|
|
|
|
|
CC |
+5 |
|
|
|
|
|
|
|
|
I |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0 |
|
|
|
|
|
|
|
|
|
±5 |
|
|
|
|
|
|
|
|
|
±10 |
|
|
|
|
|
|
|
|
|
±15 |
|
|
|
|
|
|
|
|
|
1 |
5 |
10 |
15 |
20 |
25 |
30 |
35 |
40 |
|
|
|
|
f(MHz) |
|
|
|
|
|
Figure 1. ICC vs Frequency (Worst Case) (Referenced from 15MHz)
|
6 |
|
|
|
|
|
|
5 |
|
|
|
|
|
|
4 |
|
|
|
|
|
(ns) |
3 |
|
|
|
|
|
|
|
|
|
|
|
|
PD |
2 |
|
|
|
|
|
t |
|
|
|
|
|
|
|
1 |
|
|
|
|
|
|
0 |
|
|
|
|
|
|
±1 |
|
|
|
|
|
|
±2 |
20 |
40 |
60 |
80 |
100 120 140 160 180 200 |
|
0 |
OUTPUT CAPACITANCE LOADING (pF)
Figure 2. tPD vs Output
Capacitance Loading (Typical)
October 22, 1993 |
78 |
Loading...