Philips 74HCT109N, 74HCT109DB, 74HCT109D, 74HCT109U, 74HCT109PW Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT109

Dual JK flip-flop with set and reset; positive-edge trigger

Product specification

1997 Nov 25

Supersedes data of December 1990

File under Integrated Circuits, IC06

Philips Semiconductors			Product specification

Dual JK flip-flop with set and reset;

74HC/HCT109

positive-edge trigger

FEATURES

·J, K inputs for easy D-type flip-flop

·Toggle flip-flop or “do nothing” mode

·Output capability: standard

·ICC category: flip-flops

GENERAL DESCRIPTION

The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

(SD) and reset (RD) inputs; also complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input.

The J and K inputs control the state changes of the flip-flops as described in the mode select function table.

The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The JK design allows operation as a D-type flip-flop by tying the J and K inputs together.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

SYMBOL			PARAMETER				CONDITIONS	TYPICAL		UNIT
								HC	HCT
tPHL/ tPLH	propagation delay
								15	17	ns
	nCP to nQ, nQ						CL = 15 pF;
	nSD to nQ, nQ							12	14	ns
							VCC = 5 V
	nRD to nQ, nQ							12	15	ns
fmax	maximum clock frequency							75	61	MHz
CI	input capacitance							3.5	3.5	pF
CPD	power dissipation						notes 1 and 2	20	22	pF
	capacitance per flip-flop

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V.

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

1997 Nov 25

2

Philips Semiconductors Product specification

Dual JK flip-flop with set and reset;

74HC/HCT109

positive-edge trigger

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

1, 15

1R

D, 2RD

asynchronous reset-direct input (active LOW)

2, 14, 3, 13

synchronous inputs; flip-flops 1 and 2

1J, 2J, 1K,

2K

4, 12

1CP, 2CP

clock input (LOW-to-HIGH, edge-triggered)

5, 11

1S

D, 2SD

asynchronous set-direct input (active LOW)

6, 10

1Q, 2Q

true flip-flop outputs

7, 9

complement flip-flop outputs

1Q,

2Q

8

GND

ground (0 V)

16

VCC

positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1997 Nov 25

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