Philips 74HCT253U, 74HCT253DB, 74HCT253D, 74HC253U, 74HC253N Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT253

Dual 4-input multiplexer; 3-state

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Dual 4-input multiplexer; 3-state	74HC/HCT253

FEATURES

·Non-inverting data path

·3-state outputs for bus interface

·and multiplex expansion

·Common select inputs

·Separate output enable inputs

·Output capability: bus driver

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT253 have two identical 4-input multiplexers with 3-state outputs which select two bits from four sources selected by common data select inputs (S0, S1).

When the individual output enable (1OE, 2OE) inputs of the 4-input multiplexers are HIGH, the outputs are forced to the high impedance OFF-state. The “253” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1.

The logic equations for the outputs are:

1Y = 1OE(1l0.S1.S0+1I1.S1.S0+1I2.S1.S0+1I3.S1.S0) 2Y = 2OE(2l0.S1.S0+2I1.S1.S0+2I2.S1.S0+2I3.S1.S0)

APPLICATIONS

·Data selectors

·Data multiplexers

	SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT
				HC	HCT
	tPHL/ tPLH	propagation delay	CL = 15 pF; VCC = 5 V
		1In, 2In to nY;		17	17	ns
		Sn to nY		18	19	ns
	CI	input capacitance		3.5	3.5	pF
	CPD	power dissipation capacitance per multiplexer	notes 1 and 2	55	55	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors							Product specification
Dual 4-input multiplexer; 3-state							74HC/HCT253
PIN DESCRIPTION
PIN NO.	SYMBOL					NAME AND FUNCTION
1, 15						output enable inputs (active LOW)
		1OE,	2OE
14, 2	S0, S1					common data select inputs
7, 9	1Y, 2Y					3-state multiplexer outputs
8	GND					ground (0 V)
6, 5, 4, 3	1I0 to 1I3					data inputs from source 1
10, 11, 12, 13	2I0 to 2I3					data inputs from source 2
16	VCC					positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

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