Philips 74HCT9114U, 74HCT9114N, 74HCT9114D, 74HC9114U, 74HC9114N Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT9114
Nine wide Schmitt trigger buffer; open drain outputs; inverting
Product specification |
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December 1990 |
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Supersedes data of March 1988 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Nine wide Schmitt trigger buffer;
74HC/HCT9114
open drain outputs; inverting
FEATURES
·Schmitt trigger action on all data inputs
·Output capability: standard (open drain)
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT9114 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT9114 are nine wide Schmitt trigger inverting buffer with open drain outputs and Schmitt trigger inputs.
The Schmitt trigger action in the data inputs transform slowly changing input signals into sharply defined jitter-free output signals.
The 74HC/HCT9114 have open-drain N-transistor outputs, which are not clamped by a diode connected to VCC. In the OFF-state, i.e. when one input is LOW, the output may be pulled to any voltage between GND and
VOmax. This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital
operation and OR-tied output applications, these devices must have a pull-up resistor to establish a logic HIGH level.
The “9114” is identical to the “9115” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLZ |
propagation delay An to |
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n |
CL = 15 pF; VCC = 5 V |
12 |
13 |
ns |
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Y |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per buffer |
notes 1 and 2 |
5 |
5 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors Product specification
Nine wide Schmitt trigger buffer; |
74HC/HCT9114 |
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open drain outputs; inverting |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1, 2, 3, 4, 5, 6, 7, 8, 9 |
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A0 to A8 |
data inputs |
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10 |
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GND |
ground (0 V) |
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19, 18, 17, 16, 15, 14, 13, 12, 11 |
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8 |
data outputs |
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Y |
0 to |
Y |
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20 |
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VCC |
positive supply voltage |
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lfpage |
A |
0 |
Y 0 |
19 |
lfpage |
19 |
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1 |
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1 |
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A |
1 |
Y 1 |
18 |
2 |
18 |
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2 |
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A |
2 |
Y 2 |
17 |
3 |
17 |
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3 |
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A |
3 |
Y 3 |
16 |
4 |
16 |
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4 |
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A |
4 |
Y 4 |
15 |
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5 |
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5 |
15 |
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A |
5 |
Y 5 |
14 |
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6 |
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6 |
14 |
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A |
6 |
Y 6 |
13 |
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7 |
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7 |
13 |
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A |
7 |
Y 7 |
12 |
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8 |
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8 |
12 |
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A |
8 |
Y 8 |
11 |
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9 |
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9 |
11 |
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MBA015 |
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MBA014 |
Fig.1 Pin configuration. |
Fig.2 Logic diagram. |
Fig.3 IEC logic diagram. |
December 1990 |
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