Philips 74ABT240PW, 74ABT240N, 74ABT240DB, 74ABT240D, 74ABT240-1N Datasheet

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Philips Semiconductors

Product specification

 

 

 

 

Octal inverting buffer (3-State)

74ABT240

 

 

 

 

FEATURES

Octal bus interface

3-State buffers

Output capability: +64mA/±32mA

Latch-up protection exceeds 500mA per Jedec Std 17

ESD protection exceeds 2000 V per MIL STD 883 Method 3015 and 200 V per Machine Model

Power-up 3-State

Live insertion/extraction permitted

DESCRIPTION

The 74ABT240 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

The 74ABT240 device is an octal inverting buffer that is ideal for

driving bus lines. The device features two Output Enables (1OE, 2OE), each controlling four of the 3-State outputs.

QUICK REFERENCE DATA

SYMBOL

 

 

PARAMETER

CONDITIONS

TYPICAL

UNIT

 

 

Tamb = 25°C; GND = 0V

 

 

 

 

 

 

tPLH

Propagation delay

CL = 50pF; VCC = 5V

3.1

ns

 

 

 

 

tPHL

nAx to nYx

 

 

 

CIN

Input capacitance

VI = 0V or VCC

4

pF

COUT

Output capacitance

Outputs disabled; VO = 0V or VCC

7

pF

ICCZ

Total supply current

Outputs disabled; VCC =5.5V

50

μA

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

 

 

 

 

 

20-Pin Plastic DIP

±40°C to +85°C

74ABT240 N

74ABT240 N

SOT146-1

 

 

 

 

 

20-Pin plastic SO

±40°C to +85°C

74ABT240 D

74ABT240 D

SOT163-1

 

 

 

 

 

20-Pin Plastic SSOP Type II

±40°C to +85°C

74ABT240 DB

74ABT240 DB

SOT339-1

 

 

 

 

 

20-Pin Plastic TSSOP Type I

±40°C to +85°C

74ABT240 PW

74ABT240PW DH

SOT360-1

 

 

 

 

 

PIN DESCRIPTION

 

 

PIN CONFIGURATION

 

 

 

 

 

PIN

SYMBOL

NAME AND FUNCTION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NUMBER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2, 4, 6, 8

1A0 ± 1A3

Data inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1OE

 

1

 

 

 

20

VCC

11, 13, 15,

2A0 ± 2A3

Data inputs

 

1A0

 

 

 

 

 

 

 

 

 

17

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

19

2OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18, 16, 14,

 

 

 

 

 

 

 

 

 

 

 

2Y0

3

 

 

 

18

1Y0

1Y0 ± 1Y3

Data outputs

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1A1

4

 

 

 

17

2A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9, 7, 5, 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2Y0 ± 2Y3

Data outputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2Y1

5

 

 

 

16

1Y1

1, 19

 

 

 

 

 

 

 

 

Output enables

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1OE,

2OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1A2

6

 

 

 

15

2A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

GND

Ground (0V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2Y2

7

 

 

 

14

1Y2

20

 

 

 

VCC

Positive supply voltage

 

1A3

 

 

 

 

 

2A2

 

 

 

 

8

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2Y3

9

 

 

 

12

1Y3

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

11

2A3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SA00034

1996 Sep 10

2

853±1608 17274

Philips 74ABT240PW, 74ABT240N, 74ABT240DB, 74ABT240D, 74ABT240-1N Datasheet

Philips Semiconductors

Product specification

 

 

 

Octal inverting buffer (3-State)

74ABT240

 

 

 

LOGIC SYMBOL

 

 

 

 

LOGIC SYMBOL (IEEE/IEC)

 

 

2

1A0

1Y0

18

 

1

 

 

 

 

 

 

 

 

EN

 

 

4

1A1

1Y1

16

 

 

 

 

 

6

1A2

1Y2

14

 

2

18

 

 

 

 

 

 

 

1A3

1Y3

 

 

4

16

 

 

8

12

 

6

14

 

 

 

 

 

 

 

 

 

1

1OE

 

 

 

8

12

 

 

17

2A0

2Y0

3

 

 

 

 

 

 

 

 

 

 

 

 

 

2A1

2Y1

 

 

19

EN

 

 

 

 

 

 

 

 

15

5

 

 

 

 

 

 

 

 

 

 

 

 

13

2A2

2Y2

7

 

17

3

 

 

 

 

 

 

 

11

2A3

2Y3

9

 

15

5

 

 

 

 

 

13

7

 

 

 

2OE

 

 

 

 

 

19

 

 

SA00035

11

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SA00036

FUNCTION TABLE

 

 

 

 

 

 

 

INPUTS

 

OUTPUTS

 

 

 

1OE

1An

2OE

2An

1Yn

2Yn

 

 

 

L

L

L

L

H

H

 

 

 

L

H

L

H

L

L

 

 

 

H

X

H

X

Z

Z

 

 

H

= High voltage level

 

 

 

 

 

L

= Low voltage level

 

 

 

 

 

X

= Don't care

 

 

 

 

 

 

Z = High impedance ºoffº state

ABSOLUTE MAXIMUM RATINGS1, 2

SYMBOL

PARAMETER

CONDITIONS

RATING

UNIT

 

 

 

 

 

VCC

DC supply voltage

 

±0.5 to +7.0

V

IIK

DC input diode current

VI < 0

±18

mA

V

DC input voltage3

 

±1.2 to +7.0

V

I

 

 

 

 

IOK

DC output diode current

VO < 0

±50

mA

V

DC output voltage3

output in Off or High state

±0.5 to +5.5

V

OUT

 

 

 

 

IOUT

DC output current

output in Low state

128

mA

Tstg

Storage temperature range

 

±65 to 150

°C

NOTES:

1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1996 Sep 10

3

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