Philips 74HCT32U, 74HCT32PW, 74HCT32NB, 74HCT32N, 74HCT32D Datasheet

DATA SH EET

Product specification

File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT32

Quad 2-input OR gate

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Quad 2-input OR gate 74HC/HCT32

FEATURES

• Output capability: standard

• I

CC

category: SSI

GENERAL DESCRIPTION

The 74HC/HCT32 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT32 provide the 2-input OR function.

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; t

r

=t

f

=6ns

Notes

1. C

PD

is used to determine the dynamic power dissipation (P

D

in µW):

P

D

=C

PD

× V

CC

2

× f

i

+∑(C

L

× V

CC

2

× f

o

) where:

f

i

= input frequency in MHz

f

o

= output frequency in MHz

∑ (C

L

× V

CC

2

× f

o

) = sum of outputs

C

L

= output load capacitance in pF

V

CC

= supply voltage in V

2. For HC the condition is V

I

= GND to V

CC

For HCT the condition is V

I

= GND to V

CC

− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay nA, nB to nY C

L

= 15 pF; V

CC

=5V 6 9 ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation capacitance per gate notes 1 and 2 16 28 pF