Philips 74HCT112DB, 74HCT112D, 74HCT112U, 74HCT112PW, 74HCT112N Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

Product specification

1998 Jun 10

Supersedes data of December 1990

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Dual JK flip-flop with set and reset;

74HC/HCT112

negative-edge trigger

FEATURES

·Asynchronous set and reset

·Output capability: standard

·ICC category: flip-flops

GENERAL DESCRIPTION

The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nSD) and reset (nRD) inputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs.

A HIGH level at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.

Output state changes are initiated by the HIGH-to-LOW transition of nCP.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

17

19

ns

nCP

to nQ, nQ

nS

D to nQ, nQ

15

15

ns

18

19

ns

nR

D to nQ, nQ

fmax

maximum clock frequency

66

70

MHz

CI

input capacitance

3.5

3.5

pF

CPD

power dissipation capacitance per flip-flop

notes 1 and 2

27

30

pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

1998 Jun 10

2

Philips Semiconductors	Product specification

Dual JK flip-flop with set and reset;

74HC/HCT112

negative-edge trigger

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

74HC112D;

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

74HCT112D

74HC112DB;

SSOP16

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

74HCT112DB

74HC112N;

DIP16

plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

74HCT112N

74HC112PW;

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

74HCT112PW

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

1, 13

clock input (HIGH-to-LOW, edge triggered)

1CP,

2CP

2, 12

1K, 2K

data inputs; flip-flops 1 and 2

3, 11

1J, 2J

data inputs; flip-flops 1 and 2

4, 10

1S

D, 2SD

set inputs (active LOW)

5, 9

1Q, 2Q

true flip-flop outputs

6, 7

complement flip-flop outputs

1Q,

2Q

8

GND

ground (0 V)

15, 14

D

reset inputs (active LOW)

1R

D, 2R

16

VCC

positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1998 Jun 10

3

Philips Semiconductors	Product specification

Dual JK flip-flop with set and reset;

74HC/HCT112

negative-edge trigger

FUNCTION TABLE

OPERATING MODE

INPUTS

OUTPUTS

nS

D

nRD

nCP

nJ

nK

nQ

nQ

asynchronous set

L

H

X

X

X

H

L

asynchronous reset

H

L

X

X

X

L

H

undetermined

L

L

X

X

X

H

L

toggle

H

H

↓

h

h

q

q

load “0” (reset)

H

H

↓

l

h

L

H

load “1” (set)

H

H

↓

h

l

H

L

hold “no change”

H

H

↓

l

l

q

q

Note

1. If nS

D and nRD simultaneously go from LOW to HIGH, the output states will

be unpredictable.

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP

transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP

transition

q = lower case letters indicate the state of the referenced output one set-up

time prior to the HIGH-to-LOW CP transition

Fig.4 Functional diagram.

X = don’t care

↓ = HIGH-to-LOW CP transition

Fig.5 Logic diagram (one flip-flop).

1998 Jun 10

4

Philips Semiconductors	Product specification

Dual JK flip-flop with set and reset;

74HC/HCT112

negative-edge trigger

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

ICC category: flip-flops

1998 Jun 10

5