Philips 74HCT175U, 74HCT175PW, 74HCT175NB, 74HCT175N, 74HCT175DB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT175

Quad D-type flip-flop with reset; positive-edge trigger

Product specification

1998 Jul 08

Supersedes data of December 1990

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Quad D-type flip-flop with reset; positive-edge trigger	74HC/HCT175

FEATURES

·Four edge-triggered D flip-flops

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q outputs.

The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

All Qn outputs will be forced LOW independently of clock

or data inputs by a LOW voltage level on the MR input.

The device is useful for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL

propagation delay

CL = 15 pF; VCC = 5 V

CP to Qn,

Q

n

17

16

ns

15

19

ns

MR

to Qn

tPLH

propagation delay

CP to Qn,

Q

n

17

16

ns

n

15

16

ns

MR

to

Q

fmax

maximum clock frequency

83

54

MHz

CI

input capacitance

3.5

3.5

pF

CPD

power dissipation capacitance per flip-flop

notes 1 and 2

32

34

pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

1998 Jul 08

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Philips Semiconductors									Product specification
Quad D-type flip-flop with reset; positive-edge trigger									74HC/HCT175
ORDERING INFORMATION
TYPE								PACKAGE
NUMBER			NAME					DESCRIPTION		VERSION
74HC175N;			DIP16				plastic dual in-line package; 16 leads (300 mil); long body			SOT38-1
74HCT175N
74HC175D;				SO16			plastic small outline package; 16 leads; body width 3.9 mm			SOT109-1
74HCT175D
74HC175DB;			SSOP16				plastic shrink small outline package; 16 leads; body width 5.3 mm			SOT338-1
74HCT175DB
74HC175PW;		TSSOP16					plastic thin shrink small outline package; 16 leads; body width 4.4 mm			SOT403-1
74HCT175PW
PIN DESCRIPTION
PIN NO.	SYMBOL							NAME AND FUNCTION
1								master reset input (active LOW)
		MR
2, 7, 10, 15		Q0 to Q3						flip-flop outputs
3, 6, 11, 14						3		complementary flip-flop outputs
		Q	0 to		Q
4, 5, 12, 13		D0 to D3						data inputs
8		GND						ground (0 V)
9		CP						clock input (LOW-to-HIGH, edge-triggered)
16		VCC						positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1998 Jul 08

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Philips Semiconductors	Product specification
Quad D-type flip-flop with reset; positive-edge trigger	74HC/HCT175

Fig.4

Functional diagram.

FUNCTION TABLE

OPERATING MODES

INPUTS

OUTPUTS

MR

CP

Dn

Qn

Q

n

reset (clear)

L

X

X

L

H

load “1”

H

−

h

H

L

load “0”

H

−

I

L

H

Note

1.H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition

L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition − = LOW-to-HIGH CP transition

X = don’t care

Fig.5 Logic diagram.

1998 Jul 08

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