Philips 74HCT240PW, 74HCT240N, 74HCT240DB, 74HCT240D, 74HC240U Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT240
Octal buffer/line driver; 3-state; inverting
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Octal buffer/line driver; 3-state;
74HC/HCT240
inverting
FEATURES
·Output capability: bus driver
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT240 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT240 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH on nOE causes the outputs to assume a high impedance OFF-state. The “240” is identical to the “244” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
9 |
9 |
ns |
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1An to 1Yn; |
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2An to 2Yn |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per buffer |
notes 1 and 2 |
30 |
30 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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Octal buffer/line driver; 3-state; inverting |
74HC/HCT240 |
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PIN DESCRIPTION |
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PIN NO. |
SYMBOL |
NAME AND FUNCTION |
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1 |
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output enable input (active LOW) |
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1OE |
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2, 4, 6, 8 |
1A0 to 1A3 |
data inputs |
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3, 5, 7, 9 |
2Y0 to 2Y3 |
bus outputs |
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10 |
GND |
ground (0 V) |
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17, 15, 13, 11 |
2A0 to 2A3 |
data inputs |
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18, 16, 14, 12 |
1Y0 to 1Y3 |
bus outputs |
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19 |
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output enable input (active LOW) |
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2OE |
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20 |
VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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December 1990 |
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