Philips 74HCT365U, 74HCT365NB, 74HCT365N, 74HCT365DB, 74HCT365D Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT365
Hex buffer/line driver; 3-state
Product specification |
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December 1990 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Hex buffer/line driver; 3-state |
74HC/HCT365 |
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FEATURES
·Non-inverting outputs
·Output capability: bus driver
·ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT365 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
The 74HC/HCT365 are hex non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable inputs (OE1, OE2).
A HIGH on OEn causes the outputs to assume a high impedance OFF-state.
The “365” is identical to the “366” but has non-inverting outputs.
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
9 |
11 |
ns |
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nA to nY |
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CI |
input capacitance |
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3,5 |
3,5 |
pF |
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CPD |
power dissipation capacitance per buffer |
notes 1 and 2 |
40 |
40 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990 |
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Philips Semiconductors |
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Product specification |
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Hex buffer/line driver; 3-state |
74HC/HCT365 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1, 15 |
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1, |
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2 |
output enable inputs (active LOW) |
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OE |
OE |
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2, 4, 6, 10, 12, 14 |
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1A to 6A |
data inputs |
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3, 5, 7, 9, 11, 13 |
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1Y to 6Y |
data outputs |
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8 |
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GND |
ground (0 V) |
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16 |
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VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 |
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Fig.3 IEC logic symbol. |
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December 1990 |
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