Philips 74HCT191U, 74HCT191N, 74HCT191D, 74HC191U, 74HC191PW Datasheet

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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT191

Presettable synchronous 4-bit binary up/down counter

Product speciﬁcation			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT191

up/down counter

FEATURES

∙Synchronous reversible counting

∙Asynchronous parallel load

∙Count enable control for synchronous expansion

∙Single up/down control input

∙Output capability: standard

∙ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT191 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT191 are asynchronously presettable 4-bit binary up/down counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation.

Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs (D0 to D3) is loaded into the counter

and appears on the outputs when the parallel load (PL) input is LOW. As indicated in the function table, this operation overrides the counting function.

Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The up/down (U/D) input signal determines the direction of counting as indicated in the function table. The CE input may go LOW when the clock is in either state, however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also, the U/D input should be changed only when either CE or CP is HIGH.

Overflow/underflow indications are provided by two types of outputs, the terminal count (TC) and ripple clock (RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the count-down mode or reaches “15” in the count-up-mode. The TC output will remain HIGH until a state change occurs, either by counting or presetting, or until U/D is changed. Do not use the TC output as a clock signal because it is subject to decoding spikes. The TC signal is used internally to enable the

RC output. When TC is HIGH and CE is LOW, the RC output follows the clock pulse (CP). This feature simplifies the design of multistage counters as shown in Figs 5 and 6.

In Fig.5, each RC output is used as the clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent counting in all stages, since a HIGH on CE inhibits the RC output pulse as indicated in the function table. The timing skew between state changes in the first and last stages is represented by the cumulative delay of the clock as it ripples through the preceding stages. This can be a disadvantage of this configuration in some applications.

Fig.6 shows a method of causing state changes to occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of the clock LOW state must be long enough to allow the negative-going edge of the carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no such restriction on the HIGH-state duration of the clock.

In Fig.7, the configuration shown avoids ripple delays and their associated restrictions. Combining the TC signals from all the preceding stages forms the CE input for a given stage. An enable must be included in each carry gate in order to inhibit counting. The TC output of a given stage it not affected by its own CE signal therefore the simple inhibit scheme of Figs 5 and 6 does not apply.

December 1990

Philips Semiconductors	Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT191

up/down counter

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL	PARAMETER	CONDITIONS	TYPICAL		UNIT

			HC	HCT
			HC	HCT

tPHL/ tPLH	propagation delay CP to Qn	CL = 15 pF; VCC = 5 V	22	22	ns
fmax	maximum clock frequency		36	36	MHz
CI	input capacitance		3.5	3.5	pF
CPD	power dissipation capacitance per package	notes 1 and 2	31	33	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC -1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

Philips Semiconductors	Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT191

up/down counter

PIN DESCRIPTION


PIN NO.	SYMBOL	NAME AND FUNCTION

3, 2, 6, 7	Q0 to Q3	ﬂip-ﬂop outputs
4		count enable input (active LOW)
	CE
5		up/down input
	U/D
8	GND	ground (0 V)
11		parallel load input (active LOW)
	PL
12	TC	terminal count output
13		ripple clock output (active LOW)
	RC
14	CP	clock input (LOW-to-HIGH, edge triggered)
15, 1, 10, 9	D0 to D3	data inputs
16	VCC	positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

Philips Semiconductors	Product speciﬁcation

Presettable synchronous 4-bit binary

74HC/HCT191

up/down counter

Fig.4

Functional diagram.

FUNCTION TABLE

OPERATING MODE

INPUTS

OUTPUTS

U/D

parallel load

count up

−

count up

count down

−

count down

hold (do nothing)

no change

TC AND RC FUNCTION TABLE

INPUTS

TERMINAL COUNT STATE

OUTPUTS

U/D

Notes

1.H = HIGH voltage level L = LOW voltage level

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition

X = don’t care

− = LOW-to-HIGH CP transition

= one LOW level pulse

= TC goes LOW on a LOW-to-HIGH CP transition

December 1990

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