INTEGRATED CIRCUITS
74ABT377A
Octal D-type flip-flop with enable
Product specification |
1997 Feb 26 |
Replaces data sheet 74ABT377 of 1995 Sep 06
IC23 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with enable |
74ABT377A |
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FEATURES
•Ideal for addressable register applications
•8-bit positive edge-triggered register
•Enable for address and data synchronization applications
•Output capability: +64mA/-32mA
•Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model
•Power-up reset
DESCRIPTION
The 74ABT377A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.
The 74ABT377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop's Q output.
The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25°C; GND = 0V |
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tPLH |
Propagation delay |
CL = 50pF; VCC = 5V |
3.1 |
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tPHL |
CP to Qn |
3.6 |
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CIN |
Input capacitance |
VI = 0V or VCC |
4 |
pF |
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ICCH |
Total current supply |
Outputs High; VCC = 5.5V |
500 |
nA |
ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
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OUTSIDE NORTH AMERICA |
NORTH AMERICA |
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DWG NUMBER |
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20-Pin Plastic DIP |
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±40°C to +85°C |
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74ABT377A N |
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74ABT377A N |
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SOT146-1 |
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20-Pin plastic SO |
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±40°C to +85°C |
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74ABT377A D |
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74ABT377A D |
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SOT163-1 |
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20-Pin Plastic SSOP Type II |
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±40°C to +85°C |
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74ABT377A DB |
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74ABT377A DB |
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SOT339-1 |
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20-Pin Plastic TSSOP Type I |
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±40°C to +85°C |
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74ABT377A PW |
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74ABT377PWA DH |
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SOT360-1 |
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PIN CONFIGURATION |
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LOGIC SYMBOL |
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E |
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1 |
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20 |
VCC |
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3 |
4 |
7 |
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13 |
14 |
17 |
18 |
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Q0 |
2 |
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19 |
Q7 |
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D0 |
3 |
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18 |
D7 |
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D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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D1 |
4 |
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17 |
D6 |
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11 |
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CP |
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Q1 |
5 |
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16 |
Q6 |
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Q2 |
6 |
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15 |
Q5 |
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1 |
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OE |
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D2 |
7 |
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14 |
D5 |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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D3 |
8 |
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13 |
D4 |
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Q3 |
9 |
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12 |
Q4 |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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GND |
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10 |
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11 |
CP |
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SA00155 |
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SA00152 |
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1997 Feb 26 |
2 |
853-1457 17800 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with enable |
74ABT377A |
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LOGIC SYMBOL (IEEE/IEC) |
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PIN DESCRIPTION |
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PIN NUMBER |
SYMBOL |
FUNCTION |
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1 |
E |
Enable input (active±Low) |
1 |
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3, 4, 7, 8, 13, 14, |
D0-D7 |
Data inputs |
G1 |
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11 |
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17, 18 |
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IC2 |
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2, 5, 6, 9, 12, 15, |
Q0-Q7 |
Data outputs |
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3 |
2 |
16, 19 |
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2D |
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11 |
CP |
Clock Pulse input (active |
4 |
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5 |
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rising edge) |
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7 |
6 |
10 |
GND |
Ground (0V) |
8 |
9 |
20 |
VCC |
Positive supply voltage |
13 |
12 |
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14 |
15 |
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17 |
16 |
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18 |
19 |
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SA00157 |
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LOGIC DIAGRAM
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
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3 |
4 |
7 |
8 |
13 |
14 |
17 |
18 |
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1 |
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E |
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D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
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CP |
CP |
CP |
CP |
CP |
CP |
CP |
CP |
11 |
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CP |
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2 |
5 |
6 |
9 |
12 |
15 |
16 |
19 |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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SA00158 |
1997 Feb 26 |
3 |
Philips Semiconductors |
Product specification |
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Octal D-type flip-flop with enable |
74ABT377A |
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FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING MODE |
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CP |
Dn |
Qn |
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E |
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l |
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↑ |
h |
H |
Load ª1º |
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l |
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↑ |
l |
L |
Load ª0º |
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h |
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↑ |
X |
no change |
Hold (do nothing) |
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H |
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X |
X |
no change |
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H |
= |
High voltage level |
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h |
= |
High voltage level one set-up time prior to the Low-to-High clock transition |
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L |
= |
Low voltage level |
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l |
= |
Low voltage level one set-up time prior to the Low-to-High clock transition |
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X |
= |
Don't care |
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↑ |
= |
Low-to-High clock transition |
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ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
IIK |
DC input diode current |
VI < 0 |
±18 |
mA |
V |
DC input voltage3 |
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±1.2 to +7.0 |
V |
I |
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IOK |
DC output diode current |
VO < 0 |
±50 |
mA |
V |
DC output voltage3 |
output in Off or High state |
±0.5 to +5.5 |
V |
OUT |
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IOUT |
DC output current |
output in Low state |
128 |
mA |
Tstg |
Storage temperature range |
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±65 to 150 |
°C |
NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
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LIMITS |
UNIT |
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MIN |
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MAX |
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VCC |
DC supply voltage |
4.5 |
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5.5 |
V |
VI |
Input voltage |
0 |
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VCC |
V |
VIH |
High-level input voltage |
2.0 |
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V |
VIL |
Low-level input voltage |
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0.8 |
V |
IOH |
High-level output current |
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±32 |
mA |
IOL |
Low-level output current |
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64 |
mA |
Dt/Dv |
Input transition rise or fall rate |
0 |
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5 |
ns/V |
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Tamb |
Operating free-air temperature range |
±40 |
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+85 |
°C |
1997 Feb 26 |
4 |