Philips 74HCT221N, 74HCT221DB, 74HCT221D, 74HC221N, 74HC221DB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT221

Dual non-retriggerable monostable multivibrator with reset

Product specification			December 1990
Supersedes data of April 1988
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Dual non-retriggerable monostable

74HC/HCT221

multivibrator with reset

FEATURES

·Pulse width variance is typically less than ± 5%

·Pin-out identical to “123”

·Overriding reset terminates output pulse

·nB inputs have hysteresis for improved noise immunity

·Output capability: standard (except for nREXT/CEXT)

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT221 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT221 are dual non-retriggerable monostable multivibrators. Each multivibrator features an active LOW-going edge input (nA) and an active HIGH-going edge input (nB), either of which can be used as an enable input.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry for the nB inputs allow

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

jitter-free triggering from inputs with slow transition rates, providing the circuit with excellent noise immunity.

Once triggered, the outputs (nQ, nQ) are independent of further transitions of nA and nB inputs and are a function of the timing components. The output pulses can be terminated by the overriding active LOW reset inputs (nRD). Input pulses may be of any duration relative to the output pulse.

Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications pulse stability will only be limited by the accuracy of the external timing components.

The output pulse width is defined by the following relationship:

tW = CEXTREXTIn2

tW = 0.7CEXTREXT

Pin assignments for the “221” are identical to those of the “123” so that the “221” can be substituted for those products in systems not using the retrigger by merely changing the value of REXT and/or CEXT.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

CL = 15 pF; VCC = 5 V;

tPHL

REXT = 5 kW; CEXT = 0 pF

29

32

ns

nA,

nB, nRD to nQ, nQ

tPLH

nA,

nB, nRD to nQ, nQ

35

36

ns

CI

input capacitance

3.5

3.5

pF

CPD

power dissipation capacitance per package

notes 1 and 2

90

96

pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) + 0.33 ´ CEXT ´ VCC2 ´ fo + D ´ 28 ´ VCC

where:

fi = input frequency in MHz; fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CEXT = timing capacitance in pF; CL = output load capacitance in pF

VCC = supply voltage in V; D = duty factor in %

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

December 1990

2

Philips Semiconductors	Product specification

Dual non-retriggerable monostable

74HC/HCT221

multivibrator with reset

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

PIN DESCRIPTION

PIN NO.	SYMBOL									NAME AND FUNCTION
1, 9										trigger inputs (negative-edge triggered)
	1A,		2A
2, 10	1B, 2B									trigger inputs (positive-edge triggered)
3, 11									D	direct reset inputs (active LOW)
	1R		D, 2R
4, 12										outputs (active LOW)
	1Q,		2Q
7	2REXT/CEXT									external resistor/capacitor connection
8	GND									ground (0 V)
13, 5	1Q, 2Q									outputs (active HIGH)
14, 6	1CEXT, 2CEXT									external capacitor connection
15	1REXT/CEXT									external resistor/capacitor connection
16	VCC									positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

December 1990

3

Philips Semiconductors	Product specification

Dual non-retriggerable monostable

74HC/HCT221

multivibrator with reset

FUNCTION TABLE

INPUTS

OUTPUTS

nR

D

nA

nB

nQ

nQ

L

X

X

L

H

X

H

X

L (2)

H (2)

X

X

L

L (2)

H (2)

H

L

−

H

↓

H

−

L

H

(3)

(3)

Notes

1. H = HIGH voltage level

L = LOW voltage level

X =

don’t care

− = LOW-to-HIGH level ↓ = HIGH-to-LOW level

= one HIGH-level output pulse = one LOW-level output pulse

2. If the monostable was triggered before this condition was established the pulse will continue as programmed.

3. For this combination the reset input must be LOW and the following sequence must be used:

pin 1 (or 9) must be set HIGH or pin 2 (or 10) set LOW; then pin 1 (or 9) must be LOW and pin 2 (or 10) set

Fig.4 Functional diagram. HIGH. Now the reset input goes from LOW-to-HIGH and the device will be triggered.

December 1990

4

Philips Semiconductors	Product specification

Dual non-retriggerable monostable

74HC/HCT221

multivibrator with reset

Fig.5 Logic diagram.

Note

It is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND).

Fig.6	Timing component connections.
December 1990	5