INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT132
Quad 2-input NAND Schmitt trigger
Product specification |
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September 1993 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
Product specification |
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Quad 2-input NAND Schmitt trigger |
74HC/HCT132 |
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FEATURES
·Output capability: standard
·ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the hysteresis voltage VH.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay nA, nB to nY |
CL = 15 pF; VCC = 5 V |
11 |
17 |
ns |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per gate |
notes 1 and 2 |
24 |
20 |
pF |
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2.For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993 |
2 |
Philips Semiconductors |
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Product specification |
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Quad 2-input NAND Schmitt trigger |
74HC/HCT132 |
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PIN DESCRIPTION |
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PIN NO. |
SYMBOL |
NAME AND FUNCTION |
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1, 4, 9, 12 |
1A to 4A |
data inputs |
2, 5, 10, 13 |
1B to 4B |
data inputs |
3, 6, 8, 11 |
1Y to 4Y |
data outputs |
7 |
GND |
ground (0 V) |
14 |
VCC |
positive supply voltage |
Fig.1 |
Pin configuration. |
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Fig.2 Logic symbol. |
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Fig.3 IEC logic symbol. |
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FUNCTION TABLE |
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INPUTS |
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OUTPUT |
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nA |
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nB |
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nY |
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L |
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L |
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H |
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L |
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H |
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H |
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H |
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L |
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H |
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H |
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H |
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L |
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Notes |
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1. H = HIGH voltage level |
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L = LOW voltage level |
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Fig.4 |
Functional diagram. |
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Fig.5 |
Logic diagram |
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(one Schmitt trigger). |
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APPLICATIONS |
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∙ |
Wave and pulse shapers |
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∙ |
Astable multivibrators |
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∙ |
Monostable multivibrators |
September 1993 |
3 |