Philips 74HCT273U, 74HCT273PW, 74HCT273NB, 74HCT273N, 74HCT273DB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT273

Octal D-type flip-flop with reset; positive-edge trigger

Product specification			September 1993
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Octal D-type flip-flop with reset;

74HC/HCT273

positive-edge trigger

FEATURES

·Ideal buffer for MOS microprocessor or memory

·Common clock and master reset

·Eight positive edge-triggered D-type flip-flops

·See “377” for clock enable version

·See “373” for transparent latch version

·See “374” for 3-state version

·Output capability; standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT273 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT273 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input.

The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

	SYMBOL	PARAMETER			CONDITIONS	TYPICAL		UNIT
						HC	HCT
	tPHL/ tPLH	propagation delay			CL = 15 pF; VCC = 5 V
			CP to Qn			15	15	ns
						15	20	ns
			MR	to Qn
	fmax	maximum clock frequency				66	36	MHz
	CI	input capacitance				3.5	3.5	pF
	CPD	power dissipation capacitance per flip-flop			notes 1 and 2	20	23	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

September 1993

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Philips Semiconductors Product specification

Octal D-type flip-flop with reset;				74HC/HCT273
positive-edge trigger
PIN DESCRIPTION
PIN NO.		SYMBOL		NAME AND FUNCTION
1				master reset input (active LOW)
		MR
2, 5, 6, 9, 12, 15, 16, 19		Q0 to Q7		flip-flop outputs
3, 4, 7, 8, 13, 14, 17, 18	D0 to D7			data inputs
10	GND			ground (0 V)
11	CP			clock input (LOW-to-HIGH, edge-triggered)
20	VCC			positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

September 1993

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