Philips 74HCT238U, 74HCT238PW, 74HCT238N, 74HCT238DB, 74HCT238D Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT238

3-to-8 line decoder/demultiplexer

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
3-to-8 line decoder/demultiplexer	74HC/HCT238

FEATURES

·Demultiplexing capability

·Multiple input enable for easy expansion

·Ideal for memory chip select decoding

·Active HIGH mutually exclusive outputs

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT238 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT238 decoders accept three binary weighted address inputs (A0, A1, A2) and when enabled,

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

provide 8 mutually exclusive active HIGH outputs

(Y0 to Y7).

The “238” features three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be

LOW unless E1 and E2 are LOW and E3 is HIGH.

This multiple enable function allows easy parallel expansion of the “238” to a 1-of-32 (5 lines to 32 lines) decoder with just four “238” ICs and one inverter.

The “238” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.

The “238” is identical to the “138” but has non-inverting outputs.

SYMBOL	PARAMETER			CONDITIONS		TYPICAL		UNIT
					HC		HCT
tPHL/ tPLH	propagation delay			CL = 15 pF; VCC = 5 V
		An to Yn			14		18	ns
		E3 to Yn			16		20	ns
					17		21	ns
		E	n to Yn
CI	input capacitance				3.5		3.5	pF
CPD	power dissipation capacitance per package			notes 1 and 2	72		76	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors							Product specification
3-to-8 line decoder/demultiplexer							74HC/HCT238
PIN DESCRIPTION
PIN NO.		SYMBOL				NAME AND FUNCTION
1, 2, 3		A0 to A2				address inputs
4, 5					2	enable inputs (active LOW)
		E	1,	E
6		E3				enable input (active HIGH)
8		GND				ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7		Y0 to Y7				outputs (active HIGH)
16		VCC				positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.

(a)

(b)

Fig.3 IEC logic symbol.

December 1990

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