Philips 74HCT139U, 74HCT139PW, 74HCT139NB, 74HCT139DB, 74HC139U Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT139
Dual 2-to-4 line decoder/demultiplexer
Product specification |
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September 1993 |
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File under Integrated Circuits, IC06 |
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Philips Semiconductors |
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Product specification |
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Dual 2-to-4 line decoder/demultiplexer |
74HC/HCT139 |
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FEATURES |
GENERAL DESCRIPTION |
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Demultiplexing capability |
The 74HC/HCT139 are high-speed Si-gate CMOS devices |
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Two independent 2-to-4 decoders |
and are pin compatible with low power Schottky TTL |
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(LSTTL). It is specified in compliance with JEDEC |
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Multifunction capability |
standard no. 7A. |
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Active LOW mutually exclusive outputs |
The 74HC/HCT139 are high-speed, dual 2-to-4 line |
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Output capability: standard |
decoder/multiplexers. This device has two independent |
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decoders, each accepting two binary weighted inputs |
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ICC category: MSI |
(nA0 and nA1) and providing four mutually exclusive active |
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LOW outputs (nY |
0 to nY3). Each decoder has an active |
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LOW enable input (nE) |
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is HIGH, every output is forced HIGH. The |
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When nE |
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enable can be used as the data input for a 1-to-4 demultiplexer application.
The “139” is identical to the HEF4556 of the HE4000B family.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL |
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PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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HC |
HCT |
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tPHL/ tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
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nAn to nY |
n |
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11 |
13 |
ns |
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nE |
3 to nYn |
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10 |
13 |
ns |
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CI |
input capacitance |
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3.5 |
3.5 |
pF |
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CPD |
power dissipation capacitance per multiplexer |
notes 1 and 2 |
42 |
44 |
pF |
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Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
å (CL ´ VCC2 ´ fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2.For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC - 1.5 V
APPLICATIONS
·Memory decoding or data-routing
·Code conversion
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
September 1993 |
2 |
Philips Semiconductors |
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Product specification |
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Dual 2-to-4 line decoder/demultiplexer |
74HC/HCT139 |
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PIN DESCRIPTION |
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PIN NO. |
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SYMBOL |
NAME AND FUNCTION |
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1, 15 |
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enable inputs (active LOW) |
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1E, |
2E |
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2, 3 |
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1A0, 1A1 |
address inputs |
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4, 5, 6, 7 |
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1Y |
0 to 1Y3 |
outputs (active LOW) |
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8 |
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GND |
ground (0 V) |
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12, 11, 10, 9 |
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2Y |
0 to 2Y3 |
outputs (active LOW) |
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14, 13 |
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2A0, 2A1 |
address inputs |
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16 |
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VCC |
positive supply voltage |
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Fig.1 Pin configuration. |
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Fig.2 Logic symbol. |
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(a) |
(b) |
Fig.3 IEC logic symbol.
September 1993 |
3 |
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