Philips 74HCT74U, 74HCT74PW, 74HCT74NB, 74HCT74N, 74HCT74DB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

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∙ The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

74HC/HCT74

Dual D-type flip-flop with set and reset; positive-edge trigger

Product specification

1998 Feb 23

Supersedes data of September 1993

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Dual D-type flip-flop with set and reset;

74HC/HCT74

positive-edge trigger

FEATURES

·Output capability: standard

·ICC category: flip-flops

GENERAL DESCRIPTION

The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and

Q outputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

SYMBOL				PARAMETER				CONDITIONS	TYPICAL		UNIT
									HC	HCT
tPHL/ tPLH	propagation delay							CL = 15 pF; VCC = 5 V
									14	15	ns
	nCP to nQ, nQ
	nS		D to nQ, nQ						15	18	ns
									16	18	ns
	nR		D to nQ, nQ
fmax	maximum clock frequency								76	59	MHz
CI	input capacitance								3.5	3.5	pF
CPD	power dissipation capacitance per flip-flop							notes 1 and 2	24	29	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

å (CL ´ VCC2 ´ fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

1998 Feb 23

2

Philips Semiconductors	Product specification

Dual D-type flip-flop with set and reset;

74HC/HCT74

positive-edge trigger

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
74HC(T)74N	DIP14	plastic dual in-line package; 14 leads (300 mil)	SOT27-1
74HC(T)74D	SO14	plastic small outline package; 14 leads; body width 3.9 mm	SOT108-1
74HCT74DB	SSOP14	plastic shrink small outline package; 14 leads; body width 5.3 mm	SOT337-1
74HCT74PW	TSSOP14	plastic thin shrink small outline package; 14 leads; body width 4.4 mm	SOT402-1

PIN DESCRIPTION

PIN NO.	SYMBOL									NAME AND FUNCTION
1, 13
	1R		D, 2RD							asynchronous reset-direct input (active LOW)
2, 12	1D, 2D									data inputs
3, 11	1CP, 2CP									clock input (LOW-to-HIGH, edge-triggered)
4, 10
	1S		D, 2SD							asynchronous set-direct input (active LOW)
5, 9	1Q, 2Q									true flip-flop outputs
6, 8										complement flip-flop outputs
	1Q,			2Q
7	GND									ground (0 V)
14	VCC									positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1998 Feb 23

3

Philips Semiconductors	Product specification

Dual D-type flip-flop with set and reset;

74HC/HCT74

positive-edge trigger

FUNCTION TABLE

INPUTS

OUTPUTS

S

D

R

D

CP

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

INPUTS

OUTPUTS

S

D

R

D

CP

D

Qn+1

Q

n+1

H

H

−

L

L

H

H

H

−

H

H

L

Note

1. H = HIGH voltage level L = LOW voltage level X = don’t care

− = LOW-to-HIGH CP transition

Qn+1 = state after the next LOW-to-HIGH CP transition

Fig.4 Functional diagram.

Fig.5 Logic diagram (one flip-flop).

1998 Feb 23

4