Philips 74HCT153PW, 74HCT153N, 74HCT153DB, 74HCT153D, 74HC153PW Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT153

Dual 4-input multiplexer

Product specification			December 1990
File under Integrated Circuits, IC06

Philips Semiconductors	Product specification
Dual 4-input multiplexer	74HC/HCT153

FEATURES

·Non-inverting output

·Separate enable for each output

·Common select inputs

·See ‘253” for 3-state version

·Permits multiplexing from n lines to 1 line

·Enable line provided for cascading (n lines to 1 line)

·Output capability: standard

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT153 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

The 74HC/HCT153 have two identical 4-input multiplexers which select two bits of data from up to four sources selected by common data select inputs (S0, S1). The two 4-input multiplexer circuits have individual

active LOW output enable inputs (1E,

2E) which can be used to strobe the outputs independently. The outputs (1Y, 2Y) are forced LOW when the corresponding output enable inputs are HIGH.

The “153” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1.

The logic equations for the outputs are:

1Y = 1E.(1I0.S1.S0+1I1.S1.S0+

+1I2.S1.S0+1I3.S1.S0)

2Y = 2E.(2I0.S1.S0+2I1.S1.S0+

+2I2.S1.S0+2I3.S1.S0)

The “153” can be used to move data to a common output bus from a group of registers. The state of the select inputs would determine the particular register from which the data came. An alternative application is a function generator. The device can generate two functions or three variables. This is useful for implementing highly irregular random logic.

The “153” is similar to the “253” but has standard outputs.

	SYMBOL	PARAMETER			CONDITIONS	TYPICAL		UNIT
						HC	HCT
	tPHL/ tPLH	propagation delay			CL = 15 pF; VCC = 5 V
		1In, 2In to nY				14	16	ns
		Sn to nY				15	17	ns
				to nY		10	11	ns
		nE
	CI	input capacitance				3.5	3.5	pF
	CPD	power dissipation capacitance per multiplexer			notes 1 and 2	30	30	pF

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in V

å (CL ´ VCC2 ´ fo) = sum of outputs

2.For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

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Philips Semiconductors						Product specification
Dual 4-input multiplexer						74HC/HCT153
PIN DESCRIPTION
PIN NO.	SYMBOL					NAME AND FUNCTION
1, 15						output enable inputs (active LOW)
	1E,		2E
14, 2	S0, S1					common data select inputs
6, 5, 4, 3	1I0 to 1I3					data inputs from source 1
7	1Y					multiplexer output from source 1
8	GND					ground (0 V)
9	2Y					multiplexer output from source 2
10, 11, 12, 13	2I0 to 2I3					data inputs from source 2
16	VCC					positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

Fig.4 Functional diagram.

December 1990

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