Philips 74HCT123U, 74HCT123PW, 74HCT123N, 74HCT123DB, 74HCT123D Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

∙The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT123

Dual retriggerable monostable multivibrator with reset

Product specification

1998 Jul 08

Supersedes data of September 1993

File under Integrated Circuits, IC06

Philips Semiconductors	Product specification

Dual retriggerable monostable

74HC/HCT123

multivibrator with reset

FEATURES

·DC triggered from active HIGH or active LOW inputs

·Retriggerable for very long pulses up to 100% duty factor

·Direct reset terminates output pulse

·Schmitt-trigger action on all inputs except for the reset input

·Output capability: standard (except for nREXT/CEXT)

·ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT123 are dual retriggerable monostable multivibrators with output pulse width control by three methods. The basic pulse time is programmed by selection of an external resistor

(REXT) and capacitor (CEXT). The external resistor and capacitor are

normally connected as shown in Fig.6.

Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input nRD, which also inhibits the triggering.

An internal connection from nRD to the input gates makes it possible to trigger the circuit by a positive-going signal at input nRD as shown in the function table. Figures 7 and 8 illustrate pulse control by retriggering

and early reset. The basic output pulse width is essentially determined by the values of the external timing

components REXT and CEXT. For pulse widths, when CEXT < 10 000 pF, see Fig.9.

When CEXT > 10 000 pF, the typical output pulse width is defined as:

tW = 0.45 ´ REXT ´ CEXT (typ.),

where:
tW	=	pulse width in ns;
REXT	=	external resistor in kW;
CEXT	=	external capacitor in pF.

Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower input rise and fall times.

The ‘123’ is identical to the ‘423’ but can be triggered via the reset input.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL		PARAMETER						CONDITIONS	TYPICAL		UNIT
									HC	HCT
tPHL/ tPLH	propagation delay							CL = 15 pF;
								VCC = 5 V;	26	26	ns
	nA,		nB to nQ, nQ
								REXT = 5 kW;	20	23	ns
	nRD to nQ, nQ
								CEXT = 0 pF
CI	input capacitance								3.5	3.5	pF
CPD	power dissipation
	capacitance per							notes 1 and 2	54	56	pF
	monostable

Notes

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD ´ VCC2 ´ fi + å(CL ´ VCC2 ´ fo) + 0.75 ´ CEXT ´ VCC2 ´ fo + D ´ 16 ´ VCC where:

fi = input frequency in MHz fo = output frequency in MHz D = duty factor in %

CL = output load capacitance in pF VCC = supply voltage in V

CEXT = timing capacitance in pF å (CL ´ VCC2 ´ fo) sum of outputs

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC - 1.5 V

1998 Jul 08

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Philips Semiconductors	Product specification

Dual retriggerable monostable

74HC/HCT123

multivibrator with reset

ORDERING INFORMATION

TYPE

PACKAGE

NUMBER

NAME

DESCRIPTION

VERSION

74HC123N;

DIP16

plastic dual in-line package; 16 leads (300 mil); long body

SOT38-1

74HCT123N

74HC123D;

SO16

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

74HCT123D

74HC123DB;

SSOP16

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

74HCT123DB

74HC123PW;

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

74HCT123PW

PIN DESCRIPTION

PIN NO.

SYMBOL

NAME AND FUNCTION

1, 9

trigger inputs (negative-edge triggered)

1A,

2A

2, 10

1B, 2B

trigger inputs (positive-edge triggered)

3, 11

direct reset LOW and trigger action at positive edge

1R

D, 2R

D

4, 12

outputs (active LOW)

1Q,

2Q

7

2REXT/CEXT

external resistor/capacitor connection

8

GND

ground (0 V)

13, 5

1Q, 2Q

outputs (active HIGH)

14, 6

1CEXT, 2CEXT

external capacitor connection

15

1REXT/CEXT

external resistor/capacitor connection

16

VCC

positive supply voltage

Fig.1 Pin configuration.		Fig.2 Logic symbol.		Fig.3 IEC logic symbol.

1998 Jul 08

3

Philips Semiconductors	Product specification

Dual retriggerable monostable

74HC/HCT123

multivibrator with reset

FUNCTION TABLE

INPUTS

OUTPUTS

nR

D

nA

nB

nQ

nQ

L

X

X

L

H

X

H

X

L(1)

H(1)

X

X

L

L(1)

H(1)

H

L

−

H

↓

H

−

L

H

Note

1. If the monostable was triggered

before this condition was

Fig.4 Functional diagram.

established, the pulse will

continue as programmed.

H = HIGH voltage level

L = LOW voltage level

X = don’t care

−= LOW-to-HIGH transition

↓= HIGH-to-LOW transition

= one HIGH level output pulse

= one LOW level output pulse

(1)For minimum noise generation,

it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT) externally to pin 8 (GND).

Fig.5 Logic diagram.

1998 Jul 08

4

Philips Semiconductors	Product specification

Dual retriggerable monostable

74HC/HCT123

multivibrator with reset

Fig.6 Timing component connections.

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard (except for nREXT/CEXT)

ICC category: MSI

1998 Jul 08

5

Philips Semiconductors	Product specification

Dual retriggerable monostable

74HC/HCT123

multivibrator with reset

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

													Tamb (°C)						TEST CONDITIONS
SYMBOL		PARAMETER												74HC				UNIT
																			VCC	WAVEFORMS/
											+25			−40 to +85		−40 to +125
																			(V)	NOTES
										min.	typ.	max.		min.	max.	min.	max.
	propagation delay										83	255			320		385		2.0	CEXT = 0 pF;
tPLH											30	51			64		77	ns	4.5
																				REXT = 5 kΩ
	nRD, nA, nB to nQ
											24	43			54		65		6.0
	propagation delay										83	255			320		385		2.0	CEXT = 0 pF;
tPLH											30	51			64		77	ns	4.5
																				REXT = 5 kΩ
	nRD, nA, nB to nQ
											24	43			54		65		6.0
	propagation delay										66	215			270		325		2.0	CEXT = 0 pF;
tPHL											24	43			54		65	ns	4.5
																				REXT = 5 kΩ
	nRD to nQ (reset)
											19	37			46		55		6.0
	propagation delay										66	215			270		325		2.0	CEXT = 0 pF;
tPLH											24	43			54		65	ns	4.5
																				REXT = 5 kΩ
	nRD to nQ (reset)
											19	37			46		55		6.0
	output transition										19	75			95		110		2.0
tTHL / tTLH											7	15			19		22	ns	4.5
	time
											6	13			16		19		6.0
	trigger pulse width									100	8			125		150			2.0
tW										20	3			25		30		ns	4.5	Fig.7
	nA = LOW
										17	2			21		26			6.0
	trigger pulse width									100	17			125		150			2.0
tW										20	6			25		30		ns	4.5	Fig.7
	nB = HIGH
										17	5			21		26			6.0
	reset pulse width									100	14			125		150			2.0
tW										20	5			25		30		ns	4.5	Fig.8
	nRD = LOW
										17	4			21		26			6.0
	output pulse width																			CEXT = 100 nF;
tW	nQ = HIGH										450			−		−		μs	5.0	REXT = 10 kΩ;
			= LOW																	Figs 7 and 8
	nQ
	output pulse width																			CEXT = 0 pF;
tW	nQ = HIGH										75			−		−		ns	5.0	REXT = 5 kΩ;
			= LOW																	note 1; Figs 7 and 8
	nQ
	retrigger time																			CEXT = 0 pF;
trt											110			−		−		ns	5.0	REXT = 5 kΩ;
	nA, nB
																				note 2; Fig.7
REXT	external timing									10		1000		−		−		kΩ	2.0	Fig.9
	resistor									2		1000							5.0
CEXT	external timing													no limits				pF	5.0	Fig.9; note 3
	capacitor

1998 Jul 08

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