OKI MSM514222B-60RS, MSM514222B-30ZS, MSM514222B-40JS, MSM514222B-40RS, MSM514222B-40ZS Datasheet

E2L0030-17-Y1

This version: Jan. 1998

¡SemiconductorSemiconductor MSM514222B

Previous version: Dec. 1996

MSM514222B

262,263-Word ´ 4-Bit Field Memory

DESCRIRTION

The OKI MSM514222B is a high performance 1-Mbit, 256K ´ 4-bit, Field Memory. It is designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. It is a FRAM for wide or low end use as general commodity TVs and VTRs, exclusively. The MSM514222B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture, and data storage systems and others. The 1-Mbit capacity fits one field of a conventional NTSC TV screen and cascaded directly without any delay devices among the MSM514222B. (Cascading of MSM514222B provides larger storage depth or a longer delay).

Each of the 4-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams.

The MSM514222B provides high speed FIFO, First-In First-Out, operation without external refreshing: it refreshes its DRAM storage cells automatically, so that it appears fully static to the users.

Moreover, fully static type memory cells and decoders for serial access enable refresh free serial access operation, so that the serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic.

The MSM514222B's function is simple, and similar to a digital delay device whose delay-bit- length is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings.

Additional SRAM serial registers, or line buffers for the initial access of 256 ´ 4-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings.

The MSM514222B is similar in operation and functionality to OKI 2-Mbit Field Memory MSM518222.

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MSM514222B

FEATURES

•Single power supply: 5 V ±10%

•512 Rows ´ 512 Column ´ 4 bits

•Fast FIFO (First-in First-out) operation

•High speed asynchronous serial access

Read/Write cycle time	30 ns/40 ns/60 ns
Access time	25 ns/30 ns/50 ns

•Functional compatibility with OKI MSM518222

•Self refresh (No refresh control is required)

•Package options:

16-pin 300 mil plastic DIP	(DIP16-P-300-2.54-W1)	(Product : MSM514222B-xxRS)
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27)		(Product : MSM514222B-xxJS)
20-pin 400 mil plastic ZIP	(ZIP20-P-400-1.27)	(Product : MSM514222B-xxZS)
		xx indicates speed rank.

PRODUCT FAMILY

Family	Access Time (Max.)	Cycle Time (Min.)	Package
MSM514222B-30RS	25 ns	30 ns
MSM514222B-40RS	30 ns	40 ns	300 mil 16-pin DIP
MSM514222B-60RS	50 ns	60 ns
MSM514222B-30JS	25 ns	30 ns
MSM514222B-40JS	30 ns	40 ns	300 mil 26/20-pin SOJ
MSM514222B-60JS	50 ns	60 ns
MSM514222B-30ZS	25 ns	30 ns
MSM514222B-40ZS	30 ns	40 ns	400 mil 20-pin ZIP
MSM514222B-60ZS	50 ns	60 ns

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MSM514222B

PIN CONFIGURATION (TOP VIEW)

WE				16	VCC
	1
RSTW	2			15	RE
SWCK	3			14	RSTR
DIN0	4			13	SRCK
DIN1	5			12	DOUT0
DIN2	6			11	DOUT1
DIN3	7			10	DOUT2
VSS	8			9	DOUT3
		16-Pin Plastic DIP

	WE	1	26	VCC	SRCK	1
	RSTW	2	25	RE	RE	3
	SWCK	3	24	RSTR
	DIN0	4	23	SRCK	WE	5
	NC	5	22	NC	SWCK	7
	NC	9	18	NC	NC	9
	DIN1 10		17	DOUT0	NC	11
	DIN2 11		16	DOUT1	DIN1	13
	DIN3 12		15	DOUT2
	VSS 13		14	DOUT3	DIN3	15
					DOUT3	17

26/20-Pin Plastic SOJ

DOUT1 19

2 RSTR

4 VCC

6 RSTW

8 DIN0

NO LEAD 12 NC

14 DIN2

16 VSS

18 DOUT2

20 DOUT0

20-Pin Plastic ZIP

Pin Name	Function
SWCK	Serial Write Clock
SRCK	Serial Read Clock
WE	Write Enable
RE	Read Enable
RSTW	Write Reset Clock
RSTR	Read Reset Clock
DIN0 - 3	Data Input
DOUT0 - 3	Data Output
VCC	Power Supply (5 V)
VSS	Ground (0 V)
NC	No Connection

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MSM514222B

BLOCK DIAGRAM

DOUT (´ 4)					RE	RSTR SRCK
Data-Out					Serial	Read	Controller
Buffer (´ 4)
					512 Word Serial Read Register (´ 4)
					Read Line Buffer		Read Line Buffer
					Low-Half (´ 4)		High-Half (´ 4)

		256 (´ 4)		256 (´ 4)
120 Word
Sub-Register (´ 4)		256K (´ 4)
				X	Read/Write
		Memory
				Decoder	and Refresh
		Array			Controller
120 Word
Sub-Register (´ 4)
		256 (´ 4)		256 (´ 4)	Clock
	Write Line Buffer		Write Line Buffer		Oscillator
	Low-Half (´ 4)		High-Half (´ 4)
	512 Word Serial Write Register (´ 4)
					VBB
Data-In					Generator
	Serial	Write		Controller
Buffer (´ 4)
DIN (´ 4)	WE	RSTW		SWCK

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MSM514222B

OPERATION

Write Operation

The write operation is controlled by three clocks, SWCK, RSTW, and WE. Write operation is accomplished by cycling SWCK, and holding WE high after the write address pointer reset operation or RSTW.

Each write operation, which begins after RSTW, must contain at least 130 active write cycles, i.e. SWCK cycles while WE is high. To transfer the last data to the DRAM array, which at that time is stored in the serial data registers attached to the DRAM array, an RSTW operation is required after the last SWCK cycle.

Write Reset : RSTW

The first positive transition of SWCK after RSTW becomes high resets the write address counters to zero. RSTW setup and hold times are referenced to the rising edge of SWCK. Because the write reset function is solely controlled by the SWCK rising edge after the high level of RSTW, the states of WE are ignored in the write reset cycle.

Before RSTW may be brought high again for a further reset operation, it must be low for at least two SWCK cycles.

Data Inputs : DIN0 - 3

Write Clock : SWCK

The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.

Write Enable : WE

WE is used for data write enable/disable control. WE high level enables the input, and WE low level disables the input and holds the internal write address pointer. There are no WE disable time (low) and WE enable time (high) restrictions, because the MSM514222B is in fully static operation as long as the power is on. Note that WE setup and hold times are referenced to the rising edge of SWCK.

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