OKI MSM514212-28ZS, MSM514212-34ZS, MSM514212-50ZS Datasheet

E2L0028-17-Y1

¡ Semiconductor	This version: Jan. 1998
	MSM514212
¡ Semiconductor	Previous version: Dec. 1996

MSM514212

5,048-Word ´ 8-Bit Line Memory

DESCRIPTION

The OKI MSM514212 is a high-performance serial-line memory. It is designed for use in NTSC, PAL or SECAM Video line buffer applications such as digital comb filters in TVs/VTRs, IDTV (Improved Definition Television), time based correction, or other applications that use serial data including facsimiles, digital copy machines, etc. High-reliability and low-power consumption are accomplished by using CMOS dynamic memory cells.

It has separate 8-bit-wide serial input and serial output ports that use independent data clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between input and output data streams.

A wide range of variable delay bits (40 bits to 5,048 bits) are supported offering greater design flexibility. Internal logic keeps all asynchronous accesses from being delayed by arbitrating the data storage, and data retrieval requirements to provide maximum performance at all times.

All input and output signals are TTL compatible, and the MSM514212 is packaged in a standard 400 mil 28-pin plastic ZIP.

FEATURES

•Single power supply: 5 V ±10%

•Capacity: 5,048 words ´ 8 bits

•Access: I/O asynchronous

•Access time: 28 ns (min.)

•Cycle time : 28 ns (min.)

•Delay bits: Variable (40 to 5,048)

•Low current consumption: 30 mA (max.)

•Operating voltage range: 4.5 V to 5.5 V

•Operating temperature range : 0°C to 70°C

•Package :

28-pin 400 mil plastic ZIP	(ZIP28-P-400-1.27)	(Product : MSM514212-xxZS)
		xx indicates speed rank.

PRODUCT FAMILY

Family	Cycle Time (Min.)	Access Time (Min.)	Power Dissipation (Max.)
MSM514212-28	28 ns	28 ns	230 mA
MSM514212-34	34 ns	34 ns	200 mA
MSM514212-50	50 ns	40 ns	170 mA

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¡ Semiconductor

MSM514212

PIN CONFIGURATION (TOP VIEW)

		VSS
				1					VSS
							2
		DIN3
				3					DIN2
							4
		DIN1
				5					DIN0
							6
		VCC
				7					DOUT0
							8
		DOUT1
				9					DOUT2
							10
		DOUT3
				11					VSS
							12
		RR
				13					RE
							14
		RCK
				15					VSS
							16
		DOUT4
				17					DOUT5
							18
		DOUT6
				19					DOUT7
							20
		VCC
				21					WE
							22
		WR
				23					DIN7
							24
		DIN6
				25					DIN5
							26
		DIN4
				27					WCK
							28
					28-Pin Plastic ZIP
		Pin Name				Function
		WCK				Write Clock
		WR				Write Address Reset
		WE				Write Enable
		DIN0 - 7				Data Input
		RCK				Read Clock
		RR				Read Address Reset
		RE				Read Enable
		DOUT0 - 7				Data Output
		VCC				Power Supply (5 V)
		VSS				Ground (0 V)
Note:	The same power supply voltage must be provided to every VCC pin, and the same GND
	voltage level must be provided to every VSS pin.

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	RCK	Read Timing
		Controller
	RR	Read Reset
		Controller
		Read/Write
		Select Controller
	WR	Write Reset
		Controller
	WCK	Write Timing
		Controller

DOUT0

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

Data-out

Data-out

Data-out

Data-out

Data-out

Data-out

Data-out

Data-out

RE

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

Read/Write

5032

5032

5032

5032

5032

5032

5032

5032

X

Memory

Memory

Memory

Memory

Memory

Memory

Memory

Memory

Controller

Decoder

Array

Array

Array

Array

Array

Array

Array

Array

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

32-Word

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

Data Register

VBB

Generator

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

16-Word

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Sub-Register

Data-in

Data-in

Data-in

Data-in

Data-in

Data-in

Data-in

Data-in

WE

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

Buffer

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

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DIAGRAM BLOCK

Semiconductor ¡

MSM514212

¡ Semiconductor

MSM514212

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Parameter

Symbol

Condition

Rating

Unit

Pin Voltage Relative to Vss

VT

at Ta = 25°C, Vss

–1.0 to 7.0

V

Power Supply Voltage

VCC

at Ta = 25°C, Vcc

–1.0 to 7.0

V

Circuit Output Current

I O

Ta = 25°C

20

mA

Operating Temperature

T opr

—

0 to 70

°C

Storage Temperature

T stg

—

–55 to 150

°C

Recommended Operating Conditions

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Voltage

VCC

—

4.5

5.0

5.5

V

Input High Voltage

VIH

—

2.4

—

5.5

V

Input Low Voltage

VIL

—

–1.5

—

0.8

V

Temperature Around

Ta

—

0

—

70

°C

DC Characteristics (On the Recommended Operating Conditions)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Power Supply Current

I CC

—

—

—

30

mA

Input Leakage Current

I I

VI = 0 to Vcc, Other pins are 0 V

–10

—

10

µA

Output Leakage Current

I O

VO = 0 to 5.5 V, DOUT high

–10

—

10

µA

impedance

Output High Level Voltage

VOH

IOH = –1 mA

2.4

—

—

V

Output Low Level Voltage

VOL

IOL = 2 mA

—

—

0.4

V

Capacitance

(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Input Capacitance

C I

—

—

—

5

pF

Output Capacitance

C O

—

—

—

7

pF

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¡ Semiconductor																			MSM514212
	AC Characteristics (On the Recommended Operating Conditions)
								Parameter		Symbol		-28			-34			-50		Unit
											Min.		Max.	Min.		Max.	Min.		Max.
		Write Clock Cycle Time								t WCK	28		1980	34		1980	50		1980	ns
		Write Clock Pulse Width								t WCW	11		—	14		—	20		—	ns
		Write Clock Precharge Time								t WCP	11		—	14		—	20		—	ns
		Read Clock Cycle Time								t RCK	28		1980	34		1980	50		1980	ns
		Read Clock Pulse Width								t RCW	11		—	14		—	20		—	ns
		Read Clock Precharge Time								t RCP	11		—	14		—	20		—	ns
		Access Time								t AC	—		28	—		34	—		40	ns
		Cycle Access Time Right After Reset								t ACR	—		28	—		34	—		40	ns
		Output Hold Time								t OH	5		—	5		—	5		—	ns
		Output Hold Time Right After Reset								t OHR	5		—	5		—	5		—	ns
		Output Low Impedance Period								t LZ	5		28	5		34	5		40	ns
		Output High Impedance Period								t HZ	5		28	5		34	5		40	ns
		Input Data Setup Time								t DS	11		—	14		—	15		—	ns
		Input Data Hold Time								t DH	5		—	5		—	5		—	ns
										t RS	11		—	14		—	15		—	ns
		WR/RR Setup Time from WCK/RCK
										t RH	5		—	5		—	5		—	ns
		WR/RR Hold Time from WCK/RCK
		WR/RR Nonselective Time 1 from								t RN1	5		—	5		—	5		—	ns
		WCK/RCK
		WR/RR Nonselective Time 2 from								t RN2	11		—	14		—	15		—	ns
		WCK/RCK
							Setup Time from WCK			t WES	11		—	14		—	15		—	ns
		WE
							Hold Time from WCK			t WEH	5		—	5		—	5		—	ns
		WE
							Nonselective Time 1 from WCK			t WEN1	5		—	5		—	5		—	ns
		WE
										t WEN2	11		—	14		—	15		—	ns
		WE					Nonselective Time 2 from WCK
						Setup Time from RCK				t RES	11		—	14		—	15		—	ns
		RE
						Hold Time from RCK				t REH	5		—	5		—	5		—	ns
		RE
						Nonselective Time 1 from RCK				t REN1	5		—	5		—	5		—	ns
		RE
						Nonselective Time 2 from RCK				t REN2	11		—	14		—	15		—	ns
		RE
						High Level Period				t WEW	0		—	0		—	0		—	ns
		WE
				High Level Period						t REW	0		—	0		—	0		—	ns
		RE
		WR			Low Level Period (Write Reset					t RSTW	0		—	0		—	0		—	ns
		Period)
					Low Level Period (Read Reset
		WR								t RSTR	0		—	0		—	0		—	ns
		Period)
		Transition Time								t T	3		35	3		35	3		35	ns

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