OKI MSM514252A-80JS, MSM514252A-10JS, MSM514252A-10ZS, MSM514252A-70JS, MSM514252A-70ZS Datasheet

E2L0012-17-Y1

This version: Jan. 1998

¡SemiconductorSemiconductor MSM514252A

Previous version: Dec. 1996

MSM514252A

262,144-Word ´ 4-Bit Multiport DRAM

DESCRIPTION

The MSM514252A is an 1-Mbit CMOS multiport DRAM composed of a 262,144-word by 4-bit dynamic RAM, and a 512-word by 4-bit static serial access memory, SAM port. The RAM port and SAM port operate independently and asynchronously.

The MSM514252A supports three types of operations: random access to and from the RAM port, high speed serial access to and from the SAM port and bidirectional transfer of data between any selected row in the RAM port and the SAM port. The RAM port and the SAM port can be accessed independently except when data is being transferred between them internally.

FEATURES

•Single power supply of 5 V ±10% with a built-in VBB generator

•All inputs and outputs: TTL compatible

•Multiport organization

RAM port: 256K word ´ 4 bits SAM port: 512 word ´ 4 bits

•RAM port

Fast page mode, Read-modify-write CAS before RAS refresh, Hidden refresh RAS only refresh, Standard write-per-bit

•SAM port

High speed serial Read/Write capability Fully static register 512 tap location

•RAM-SAM bidirectional, Read/Write/Pseudo write, Real time read transfer

•Package options:

28-pin 400 mil plastic ZIP	(ZIP28-P-400-1.27)	(Product : MSM514252A-xxZS)
28-pin 400 mil plastic SOJ	(SOJ28-P-400-1.27)	(Product : MSM514252A-xxJS)
		xx indicates speed rank.

PRODUCT FAMILY

	Family	Access Time		Cycle Time		Power Dissipation
		RAM	SAM	RAM	SAM	Operating	Standby
	MSM514252A-70	70 ns	25 ns	140 ns	30 ns	120 mA	8 mA
	MSM514252A-80	80 ns	25 ns	150 ns	30 ns	110 mA	8 mA
	MSM514252A-10	100 ns	25 ns	180 ns	30 ns	100 mA	8 mA

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	¡ Semiconductor						MSM514252A
	PIN CONFIGURATION (TOP VIEW)
	NC	1	W3/IO3	SC	1	28	VSS
		2		SIO1	2	27	SIO4
	W4/IO4	3	SE
		4		SIO2	3	26	SIO3
	SIO3	5
			SIO4	DT/OE	4	25	SE
		6
	VSS	7	SC	W1/IO1	5	24	W4/IO4
		8		W2/IO2	6	23	W3/IO3
	SIO1	9	SIO2
		10		WB/WE 7		22	NC
	DT/OE	11
							CAS
	W2/IO2	12	W1/IO1	NC	8	21
		13	WB/WE	RAS 9		20	NC
		14
	NC	15	RAS	A8	10	19	A0
		16		A6	11	18	A1
	A8	17	A6
		18		A5	12	17	A2
	A5	19
			A4	A4	13	16	A3
		20
	VCC	21	A7	VCC 14		15	A7
		22
	A3	23

			24		A2
	A1				28-Pin Plastic SOJ
		25
			26		A0
	NC
		27			CAS
			28

28-Pin Plastic ZIP

Pin Name	Function
A0 - A8	Address Input
RAS	Row Address Strobe
CAS	Column Address Strobe
DT/OE	Data Transfer/Output Enable
WB/WE	Write per Bit/Write Enable
W1/IO1 - W4/IO4	Write Mask/Data IN, OUT
SC	Serial Clock
SE	Serial Enable
SIO1 - SIO4	Serial Input/Output
VCC/VSS	Power Supply (5 V) /Ground (0 V)
NC	No Connection

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¡ Semiconductor							MSM514252A
BLOCK DIAGRAM
W1/IO1 - W4/IO4	RAS	CAS	DT/OE	WB/WE	SC	SE	SIO1 - SIO4
I/O Buffer			Timing Generator				I/O Buffer
(RAM)							(SAM)

Mask Register

Write/WPB Control

DecoderColumn	AmplifierSense		512	´ 512	´ 4
			Cell Array

Row Decoder

Column			Row					Refresh
Address			Address
								Counter
Buffer			Buffer

A0 - A8

	SAM	Selector

Serial	Address		Counter

VCC

VSS

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¡ Semiconductor MSM514252A

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

				(Note : 16)
Parameter	Symbol	Condition	Rating	Unit
Input Output Voltage	VT	Ta = 25°C	–1.0 to 7.0	V
Output Current	lOS	Ta = 25°C	50	mA
Power Dissipation	PD	Ta = 25°C	1	W
Operating Temperature	Topr	—	0 to 70	°C
Storage Temperature	Tstg	—	–55 to 150	°C

Recommended Operating Conditions

(Ta = 0°C to 70°C) (Note : 17)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Power Supply Voltage

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.4

—

6.5

V

Input Low Voltage

VIL

–1.0

—

0.8

V

Capacitance

(VCC = 5 V ±10%, f = 1 MHz, Ta = 25°C)

Parameter

Symbol

Min.

Max.

Unit

Input Capacitance

CI

—

7

pF

Input / Output Capacitance

CI/O

—

9

pF

Note : This parameter is periodically sampled and is not 100% tested.

DC Characteristics 1

Parameter

Symbol

Condition

Min.

Max.

Unit

Output "H" Level Voltage

VOH

IOH = –2 mA

2.4

—

V

Output "L" Level Voltage

VOL

IOL = 2 mA

—

0.4

Input Leakage Current

ILI

0 £ VIN £ VCC

–10

10

All other pins

not under test = 0 V

mA

Output Leakage Current

ILO

0 £ VOUT £ 5.5 V

–10

10

Output Disable

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	¡ Semiconductor					MSM514252A
	DC Characteristics 2			(VCC = 5 V ±10%, Ta = 0°C to 70°C)
	Item (RAM)	SAM	Symbol	-70	-80	-10	Unit	Note
				Max.	Max.	Max.
	Operating Current	Standby	ICC1	85	75	65		1, 2
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC1A	120	110	100		1, 2
	Standby Current	Standby	ICC2	8	8	8		3
	(RAS, CAS = VIH)	Active	ICC2A	50	45	40		1, 2
	RAS Only Refresh Current	Standby	ICC3	85	75	65		1, 2
	(RAS Cycling, CAS = VIH, tRC = tRC min.)	Active	ICC3A	120	110	100	mA	1, 2
	Page Mode Current	Standby	ICC4	70	65	60		1, 2
	(RAS = VIL, CAS Cycling, tPC = tPC min.)	Active	ICC4A	120	110	100		1, 2
	CAS before RAS Refresh Current	Standby	ICC5	85	75	65		1, 2
	(RAS Cycling, CAS before RAS, tRC = tRC min.)	Active	ICC5A	120	110	100		1, 2
	Data Transfer Current	Standby	ICC6	85	75	65		1, 2
	(RAS, CAS Cycling, tRC = tRC min.)	Active	ICC6A	120	110	100		1, 2

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	¡ Semiconductor							MSM514252A
	AC Characteristics (1/3)		(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
	Parameter	Symbol	-70		-80		-10		Unit	Note
			Min.	Max.	Min.	Max.	Min.	Max.
	Random Read or Write Cycle Time	tRC	140	—	150	—	180	—	ns
	Read Modify Write Cycle Time	tRWC	195	—	195	—	235	—	ns
	Fast Page Mode Cycle Time	tPC	45	—	50	—	55	—	ns
	Fast Page Mode Read Modify Write Cycle Time	tPRWC	90	—	90	—	100	—	ns
	Access Time from RAS	tRAC	—	70	—	80	—	100	ns	7, 13
	Access Time from Column Address	tAA	—	35	—	40	—	50	ns	7, 13
	Access Time from CAS	tCAC	—	20	—	25	—	25	ns	7, 14
	Access Time from CAS Precharge	tCPA	—	40	—	45	—	50	ns	7, 14
	Output Buffer Turn-off Delay	tOFF	0	20	0	20	0	20	ns	9
	Transition Time (Rise and Fall)	tT	3	35	3	35	3	35	ns	6
	RAS Precharge Time	tRP	60	—	60	—	70	—	ns
	RAS Pulse Width	tRAS	70	10k	80	10k	100	10k	ns
	RAS Pulse Width (Fast Page Mode Only)	tRASP	70	100k	80	100k	100	100k	ns
	RAS Hold Time	tRSH	20	—	25	—	25	—	ns
	CAS Hold Time	tCSH	70	—	80	—	100	—	ns
	CAS Pulse Width	tCAS	20	10k	25	10k	25	10k	ns
	RAS to CAS Delay Time	tRCD	20	50	20	55	20	75	ns	13
	RAS to Column Address Delay Time	tRAD	15	35	15	40	20	50	ns	13
	Column Address to RAS Lead Time	tRAL	35	—	40	—	55	—	ns
	CAS to RAS Precharge Time	tCRP	10	—	10	—	10	—	ns
	CAS Precharge Time	tCPN	10	—	10	—	10	—	ns
	CAS Precharge Time (Fast Page Mode)	tCP	10	—	10	—	10	—	ns
	Row Address Set-up Time	tASR	0	—	0	—	0	—	ns
	Row Address Hold Time	tRAH	10	—	10	—	10	—	ns
	Column Address Set-up Time	tASC	0	—	0	—	0	—	ns
	Column Address Hold Time	tCAH	15	—	15	—	15	—	ns
	Column Address Hold Time referenced to RAS	tAR	55	—	55	—	70	—	ns
	Read Command Set-up Time	tRCS	0	—	0	—	0	—	ns
	Read Command Hold Time	tRCH	0	—	0	—	0	—	ns	10
	Read Command Hold Time referenced to RAS	tRRH	0	—	0	—	0	—	ns	10
	Write Command Hold Time	tWCH	15	—	15	—	15	—	ns
	Write Command Hold Time referenced to RAS	tWCR	55	—	55	—	70	—	ns
	Write Command Pulse Width	tWP	15	—	15	—	15	—	ns
	Write Command to RAS Lead Time	tRWL	20	—	20	—	25	—	ns
	Write Command to CAS Lead Time	tCWL	20	—	20	—	25	—	ns

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	¡ Semiconductor							MSM514252A
	AC Characteristics (2/3)		(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
	Parameter	Symbol	-70		-80		-10		Unit	Note
			Min.	Max.	Min.	Max.	Min.	Max.
	Data Set-up Time	tDS	0	—	0	—	0	—	ns	11
	Data Hold Time	tDH	15	—	15	—	15	—	ns	11
	Data Hold Time referenced to RAS	tDHR	55	—	55	—	70	—	ns
	Write Command Set-up Time	tWCS	0	—	0	—	0	—	ns	12
	RAS to WE Delay Time	tRWD	100	—	100	—	130	—	ns	12
	Column Address to WE Delay Time	tAWD	65	—	65	—	80	—	ns	12
	CAS to WE Delay Time	tCWD	45	—	45	—	55	—	ns	12
	Data to CAS Delay Time	tDZC	0	—	0	—	0	—	ns
	Data to OE Delay Time	tDZO	0	—	0	—	0	—	ns
	Access Time from OE	tOEA	—	20	—	20	—	25	ns	7
	Output Buffer Turn-off Delay from OE	tOEZ	0	10	0	10	0	20	ns	9
	OE to Data Delay Time	tOED	10	—	10	—	20	—	ns
	OE Command Hold Time	tOEH	10	—	10	—	20	—	ns
	RAS Hold Time referenced to OE	tROH	15	—	15	—	15	—	ns
	CAS Set-up Time for CAS before RAS Cycle	tCSR	10	—	10	—	10	—	ns
	CAS Hold Time for CAS before RAS Cycle	tCHR	10	—	10	—	10	—	ns
	RAS Precharge to CAS Active Time	tRPC	0	—	0	—	0	—	ns
	Refresh Period	tREF	—	8	—	8	—	8	ms
	WB Set-up Time	tWSR	0	—	0	—	0	—	ns
	WB Hold Time	tRWH	15	—	15	—	15	—	ns
	Write Per Bit Mask Data Set-up Time	tMS	0	—	0	—	0	—	ns
	Write Per Bit Mask Data Hold Time	tMH	15	—	15	—	15	—	ns
	DT High Set-up Time	tTHS	0	—	0	—	0	—	ns
	DT High Hold Time	tTHH	15	—	15	—	15	—	ns
	DT Low Set-up Time	tTLS	0	—	0	—	0	—	ns
	DT Low Hold Time	tTLH	15	10k	15	10k	15	10k	ns
	DT Low Hold Time referenced to RAS	tRTH	60	10k	65	10k	80	10k	ns
	(Real Time Read Transfer)
	DT Low Hold Time referenced to Column Address	tATH	25	—	30	—	30	—	ns
	(Real Time Read Transfer)
	DT Low Hold Time referenced to CAS	tCTH	20	—	25	—	25	—	ns
	(Real Time Read Transfer)
	SE Set-up Time referenced to RAS	tESR	0	—	0	—	0	—	ns
	SE Hold Time referenced to RAS	tREH	15	—	15	—	15	—	ns
	DT to RAS Precharge Time	tTRP	60	—	60	—	70	—	ns
	DT Precharge Time	tTP	20	—	20	—	30	—	ns
	RAS to First SC Delay Time (Read Transfer)	tRSD	70	—	80	—	100	—	ns
	Column Address to First SC Delay Time (Read Transfer)	tASD	45	—	45	—	50	—	ns
	CAS to First SC Delay Time (Read Transfer)	tCSD	20	—	25	—	25	—	ns
	Last SC to DT Lead Time (Real Time Read Transfer)	tTSL	5	—	5	—	5	—	ns

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	¡ Semiconductor										MSM514252A
	AC Characteristics (3/3)		(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 4, 5, 6
	Parameter	Symbol		-70		-80				-10		Unit	Note
			Min.		Max.	Min.	Max.		Min.		Max.
	DT to First SC Delay Time (Read Transfer)	tTSD	15		—	15		—	15		—	ns
	Last SC to RAS Set-up Time (Serial Input)	tSRS	25		—	25		—	30		—	ns
	RAS to First SC Delay Time (Serial Input)	tSRD	20		—	20		—	25		—	ns
	RAS to Serial Input Delay Time	tSDD	40		—	40		—	50		—	ns
	Serial Output Buffer Turn-off Delay from RAS	tSDZ	10		40	10		40	10		50	ns	9
	(Pseudo Write Transfer)
	SC Cycle Time	tSCC	30		—	30		—	30		—	ns
	SC Pulse Width (SC High Time)	tSC	10		—	10		—	10		—	ns
	SC Precharge Time (SC Low Time)	tSCP	10		—	10		—	10		—	ns
	Access Time from SC	tSCA	—		25	—		25	—		25	ns	8
	Serial Output Hold Time from SC	tSOH	5		—	5		—	5		—	ns
	Serial Input Set-up Time	tSDS	0		—	0		—	0		—	ns
	Serial Input Hold Time	tSDH	15		—	15		—	15		—	ns
	Access Time from SE	tSEA	—		25	—		25	—		25	ns	8
	SE Pulse Width	tSE	25		—	25		—	25		—	ns
	SE Precharge Time	tSEP	25		—	25		—	25		—	ns
	Serial Output Buffer Turn-off Delay from SE	tSEZ	0		20	0		20	0		20	ns	9
	Serial Input to SE Delay Time	tSZE	0		—	0		—	0		—	ns
	Serial Input to First SC Delay Time	tSZS	0		—	0		—	0		—	ns
	Serial Write Enable Set-up Time	tSWS	5		—	5		—	5		—	ns
	Serial Write Enable Hold Time	tSWH	15		—	15		—	15		—	ns
	Serial Write Disable Set-up Time	tSWIS	5		—	5		—	5		—	ns
	Serial Write Disable Hold Time	tSWIH	15		—	15		—	15		—	ns

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¡ Semiconductor MSM514252A

Notes: 1. These parameters depend on output loading. Specified values are obtained with the

output open.

2.These parameters are masured at minimum cycle test.

3.ICC2 (Max.) are mesured under the condition of TTL input level.

4.VIH (Min.) and VIL (Max.) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL.

5.An initial pause of 200 ms is required after power-up followed by any 8 RAS cycles (DT/OE “high”) and any 8 SC cycles before proper divice operation is achieved. In the case of using an internal refresh counter, a minimum of 8 CAS before RAS initialization cycles in stead of 8 RAS cycles are required.

6.AC measurements assume tT = 5 ns.

7.RAM port outputs are mesured with a load equivalent to 1 TTL load and 100 pF. Output reference levels are VOH/VOL = 2.4 V/0.8 V.

8.SAM port outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output reference levels are VOH/VOL = 2.0 V/0.8 V.

9.tOFF (Max.), tOEZ (Max.), tSDZ (Max.) and tSEZ (Max.) difine the time at which the outputs achieve the open circuit condition and are not reference to output voltage levels.

10.Either tRCH or tRRH must be satisfied for a read cycle.

11.These parameters are referenced to CAS leading edge of early write cycles and to WB/WE leading edge in OE controlled write cycles and read modify write cycles.

12.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only.

If tWCS ≥ tWCS (Min.), the cycle is an early write cycle, and the data out pin will remain open circuit (high impedance) throughout the entire cycle : If tRWD ≥ tRWD (Min.), tCWD ≥ tCWD (Min.) and tAWD ≥ tAWD (Min.) the cycle is a read-write cycle and the data out will contain data read from the selected cell : If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indterminate.

13.Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only : If tRCD is greater than the specified tRCD (Max.) limit, then access time is controlled by tCAC.

14.Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only : If tRAD is greater than the specified tRAD (Max.) limit, then access time is controlled by tAA.

15.Input levels at the AC parameter measurement are 3.0 V/0 V.

16.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permenent damege to the device.

17.All voltages are referenced to VSS.

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¡ Semiconductor

MSM514252A

TIMING WAVEFORM

Read Cycle

RAS VIH –

VIL –

CAS VIH –

VIL –

VIH –

A0 - A8

VIL –

WB/WE VIH –

VIL –

DT/OE VIH –

VIL –

VIH –

IN VIL –

W1/IO1

- W4/IO4

VOH –

OUT

VOL –

			tRC
		tRAS		tRP
		tAR
		tCSH
tCRP		tRCD	tRSH	tCPN
			tCAS
	tRAD		tRAL
tASR	tRAH	tASC	tCAH
Row Address		Column Address
		tRCS		tRCH
				tRRH
tTHS	tTHH		tROH
	tDZO		tOEA
		tAA	tCAC	tOFF
				tOEZ
	tRAC
		Open		Valid Data-out

"H" or "L"

10/33