DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions.
MODE SELECT Ð TRUTH TABLE
OPERATING MODE |
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INPUTS |
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OUTPUTS |
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S |
D |
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C |
D |
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J |
K |
Q |
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Q |
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Set |
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L |
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H |
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X |
X |
H |
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L |
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Reset (Clear) |
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H |
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L |
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X |
X |
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L |
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H |
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*Undetermined |
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L |
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L |
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X |
X |
H |
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H |
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Toggle |
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H |
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H |
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h |
h |
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q |
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q |
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Load ª0º (Reset) |
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H |
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H |
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l |
h |
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L |
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H |
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Load ª1º (Set) |
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H |
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H |
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h |
l |
H |
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L |
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Hold |
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H |
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H |
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l |
l |
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q |
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q |
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*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the HIGH-to-LOW clock transition
LOGIC DIAGRAM
Q
CLEAR (CD) 
J 
Q |
SET (SD) |
K |
CLOCK (CP)
SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
LOW POWER SCHOTTKY
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J SUFFIX |
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CERAMIC |
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CASE 620-09 |
16 |
1 |
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N SUFFIX |
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PLASTIC |
16 |
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CASE 648-08 |
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1 |
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D SUFFIX |
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16 |
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SOIC |
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CASE 751B-03 |
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1 |
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ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC SYMBOL
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2 |
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7 |
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16 |
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K |
SD Q |
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15 |
12 |
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K |
S |
D |
Q |
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11 |
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1 |
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CP |
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6 |
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CP |
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4 |
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J |
C |
Q |
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14 |
9 |
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J |
C |
Q |
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10 |
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D |
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D |
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3 |
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8 |
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VCC = PIN 5 |
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GND = PIN 13 |
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FAST AND LS TTL DATA
5-79
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