MOTOROLA SN74LS175D, SN74LS175DR2, SN74LS175M, SN74LS175MEL, SN74LS175ML1 Datasheet
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SN74LS175
Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.
•Edge-Triggered D-Type Inputs
•Buffered-Positive Edge-Triggered Clock
•Clock to Output Delays of 30 ns
•Asynchronous Common Reset
•True and Complement Output
•Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
4.75 |
5.0 |
5.25 |
V |
TA |
Operating Ambient |
0 |
25 |
70 |
°C |
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Temperature Range |
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IOH |
Output Current ± High |
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± 0.4 |
mA |
IOL |
Output Current ± Low |
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8.0 |
mA |
http://onsemi.com
LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device |
Package |
Shipping |
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SN74LS175N |
16 Pin DIP |
2000 Units/Box |
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SN74LS175D |
16 Pin |
2500/Tape & Reel |
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Semiconductor Components Industries, LLC, 1999 |
1 |
Publication Order Number: |
December, 1999 ± Rev. 6 |
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SN74LS175/D |
SN74LS175
CONNECTION DIAGRAM DIP (TOP VIEW)
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VCC |
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Q3 |
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Q3 |
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D3 |
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D2 |
Q2 |
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Q2 |
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CP |
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16 |
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NOTE: |
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The Flatpak version has the same |
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pinouts (Connection Diagram) as |
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the Dual In-Line Package. |
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Q0 |
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D0 |
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D1 |
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1 |
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Q1 |
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GND |
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MR |
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Q |
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Q |
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LOADING (Note a) |
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PIN NAMES |
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HIGH |
LOW |
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D0 ± D3 |
Data Inputs |
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0.5 U.L. |
0.25 U.L. |
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CP |
Clock (Active HIGH Going Edge) Input |
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0.5 U.L. |
0.25 U.L. |
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Master Reset (Active LOW) Input |
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0.5 U.L. |
0.25 U.L. |
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MR |
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Q0 ± Q3 |
True Outputs |
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10 U.L. |
5 U.L. |
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Q |
0 ± |
Q |
3 |
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Complemented Outputs |
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10 U.L. |
5 U.L. |
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NOTES: |
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a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC SYMBOL
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4 |
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5 |
12 |
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13 |
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9 |
CP |
D0 |
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D1 |
D2 |
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D3 |
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MR |
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Q0 Q0 Q1 Q1 Q2 |
Q2 Q3 Q3 |
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3 |
2 |
6 |
7 |
11 |
10 |
14 |
15 |
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VCC = PIN 16 |
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GND = PIN 8 |
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LOGIC DIAGRAM |
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MR |
CP |
D3 |
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D2 |
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D1 |
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D0 |
1 |
9 |
13 |
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12 |
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5 |
4 |
D Q |
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D Q |
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D Q |
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D Q |
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CP Q |
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CP Q |
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CP Q |
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CP Q |
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CD |
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CD |
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CD |
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CD |
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14 |
15 |
11 |
10 |
6 |
7 |
3 |
2 |
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Q3 Q3 |
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Q2 Q2 |
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Q1Q1 |
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Q0 Q0 |
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
http://onsemi.com
2
SN74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs.
The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
TRUTH TABLE
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Inputs (t = n, MR = H) |
Outputs (t = n+1) Note 1 |
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D |
Q |
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Q |
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L |
L |
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H |
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H |
H |
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L |
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Note 1: t = n + 1 indicates conditions after next clock.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
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Limits |
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Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
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Test Conditions |
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VIH |
Input HIGH Voltage |
2.0 |
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V |
Guaranteed Input HIGH Voltage for |
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All Inputs |
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VIL |
Input LOW Voltage |
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0.8 |
V |
Guaranteed Input LOW Voltage for |
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All Inputs |
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VIK |
Input Clamp Diode Voltage |
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± 0.65 |
± 1.5 |
V |
VCC = MIN, IIN = ± 18 mA |
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VOH |
Output HIGH Voltage |
2.7 |
3.5 |
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V |
VCC = MIN, IOH = MAX, VIN = VIH |
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or VIL per Truth Table |
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0.25 |
0.4 |
V |
I = 4.0 mA |
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VCC = VCC MIN, |
VOL |
Output LOW Voltage |
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OL |
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VIN = VIL or VIH |
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0.35 |
0.5 |
V |
IOL = 8.0 mA |
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per Truth Table |
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IIH |
Input HIGH Current |
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20 |
μA |
VCC = MAX, VIN = 2.7 V |
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0.1 |
mA |
VCC = MAX, VIN = 7.0 V |
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IIL |
Input LOW Current |
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± 0.4 |
mA |
VCC = MAX, VIN = 0.4 V |
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IOS |
Short Circuit Current (Note 1) |
± 20 |
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± 100 |
mA |
VCC = MAX |
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ICC |
Power Supply Current |
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18 |
mA |
VCC = MAX |
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Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
http://onsemi.com
3
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