Motorola SN54LS192J, SN54LS193J, SN74LS192D, SN74LS192N, SN74LS193D Datasheet

PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.

Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.

•Low Power . . . 95 mW Typical Dissipation

•High Speed . . . 40 MHz Typical Count Frequency

•Synchronous Counting

•Asynchronous Master Reset and Parallel Load

•Individual Preset Inputs

•Cascading Circuitry Internally Provided

•Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC			P0		MR	TCD		TCU			PL		P2		P3
	16		15		14		13		12		11		10		9

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

1

2

3

4

5

6

7

8

P1

Q1

Q0

CPD

CPU

Q2

Q3

GND

PIN NAMES		LOADING (Note a)
		HIGH		LOW
	Count Up Clock Pulse Input
CPU		0.5	U.L.	0.25	U.L.
CPD	Count Down Clock Pulse Input	0.5	U.L.	0.25	U.L.
MR	Asynchronous Master Reset (Clear) Input	0.5	U.L.	0.25	U.L.
PL	Asynchronous Parallel Load (Active LOW) Input	0.5	U.L.	0.25	U.L.
Pn	Parallel Data Inputs	0.5	U.L.	0.25	U.L.
Qn	Flip-Flop Outputs (Note b)	10	U.L.	5 (2.5)	U.L.
TCD	Terminal Count Down (Borrow) Output (Note b)	10	U.L.	5 (2.5)	U.L.
TCU	Terminal Count Up (Carry) Output (Note b)	10	U.L.	5 (2.5)	U.L.

NOTES:

a.1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

b.The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b.Temperature Ranges.

SN54/74LS192

SN54/74LS193

PRESETTABLE BCD/DECADE

UP/DOWN COUNTER

PRESETTABLE 4-BIT BINARY

UP/DOWN COUNTER

LOW POWER SCHOTTKY

			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

LOGIC SYMBOL

11 15 1 10 9

PL

P0

P1

P2

P3

12

5

CPU

TCU

4

CPD

TC

13

D

MR Q0

Q1

Q2

Q3

7

14

3

2

6

VCC = PIN 16

GND =

PIN

8

FAST AND LS TTL DATA

5-351

SN54/74LS192 •SN54/74LS193

STATE DIAGRAMS
0	1	2	3	4	LS192 LOGIC EQUATIONS
					FOR TERMINAL COUNT
15				5	TCU = Q0 Q3 CPU
					TCD = Q0 Q1 Q2 Q3 CPD

14				6	LS193 LOGIC EQUATIONS
					FOR TERMINAL COUNT
13				7	TCU = Q0	Q1 Q2 Q3 CPU
					TCD = Q0	Q1 Q2 Q3 CPD
12	11	10	9	8
					COUNT	UP
		LS192			COUNT	DOWN

0	1	2	3	4
15				5
14				6
13				7
12	11	10	9	8

LS193

LOGIC DIAGRAMS
				P0	P1	P2	P3
	PL		11	15	1	10	9
	(LOAD)		5
	CPU						12	TCU
(UP	COUNT)							(CARRY
								OUTPUT)
				SD Q	SD Q	SD Q	SD Q
				T	T	T	T
				CDQ	CDQ	CDQ	CDQ
							13	TCD
	CPD		4					(BORROW
								OUTPUT)
	(DOWN
	COUNT)		14
	MR
	(CLEAR)			3	2	6	7
				Q0	Q1	Q2	Q3
VCC = PIN 16					LS192
GND		=	PIN	8
	=	PIN		NUMBERS

FAST AND LS TTL DATA

5-352

SN54/74LS192 •SN54/74LS193

LOGIC DIAGRAMS (continued)
				P0	P1	P2	P3
	PL	11		15	1	10	9
	(LOAD)	5
	CPU						12	TC
(UP	COUNT)							U
								(CARRY
								OUTPUT)
				SD Q	SDQ	SD Q	SD Q
				T	T	T	T
				CDQ	CDQ	CDQ	CDQ
							13	TCD
	CPD	4						(BORROW
								OUTPUT)
	(DOWN
	COUNT)	14
	MR
	(CLEAR)			3	2	6	7
				Q0	Q1	Q2	Q3
					LS193
	VCC = PIN 16
	GND	=	PIN	8
	=	PIN		NUMBERS

FAST AND LS TTL DATA

5-353