Motorola SN54LS194AJ, SN74LS194AN, SN74LS194AD Datasheet

4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

The SN54 /74LS194A is a High Speed 4-Bit Bidirectional Universal Shift Register. As a high speed multifunctional sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift Register, with added features of shift left without external connections and hold (do nothing) modes of operation. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all Motorola TTL families.

•Typical Shift Frequency of 36 MHz

•Asynchronous Master Reset

•Hold (Do Nothing) Mode

•Fully Synchronous Serial or Parallel Data Transfers

•Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC			Q0		Q1		Q2		Q3		CP		S1		S0
	16		15		14		13		12		11		10		9

	1		2		3		4		5		6		7		8
	MR		DSR		P0		P1		P2		P3		DSL		GND

PIN NAMES		LOADING (Note a)
		HIGH		LOW
S0, S1	Mode Control Inputs	0.5	U.L.	0.25	U.L.
P0 ± P3	Parallel Data Inputs	0.5	U.L.	0.25	U.L.
DSR	Serial (Shift Right) Data Input	0.5	U.L.	0.25	U.L.
DSL	Serial (Shift Left) Data Input	0.5	U.L.	0.25	U.L.
CP	Clock (Active HIGH Going Edge) Input	0.5	U.L.	0.25	U.L.
MR	Master Reset (Active LOW) Input	0.5	U.L.	0.25	U.L.
Q0 ± Q3	Parallel Outputs (Note b)	10	U.L.	5 (2.5)	U.L.

NOTES:

a.1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

b.The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b.Temperature Ranges.

SN54/74LS194A

4-BIT BIDIRECTIONAL

UNIVERSAL SHIFT REGISTER

LOW POWER SCHOTTKY

			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

FAST AND LS TTL DATA

5-360

SN54/74LS194A

LOGIC DIAGRAM

			P0		P1		P2			P3
		10	3		4		5			6
S1
		9
S0
		2									7
DSR											DSL
VCC = PIN 16
GND	=	PIN	8
=		PIN	NUMBERS	S	Q0	S	Q1	S	Q2	S	Q3
				CP		CP		CP		CP
				R		R		R		R
				CLEAR		CLEAR		CLEAR		CLEAR
		11
CP
		1
MR
					15		14		13		12
					Q0		Q1		Q2		Q3

FUNCTIONAL DESCRIPTION

The Logic Diagram and Truth Table indicate the functional characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the Motorola LS195A Universal Shift Register when used in serial or parallel data register transfers. Some of the common features of the two devices are described below:

All data and mode control inputs are edge-triggered, responding only to the LOW to HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse.

The register is fully synchronous, with all operations taking place in less than 15 ns (typical) making the device especially useful for implementing very high speed CPUs, or the memory buffer registers.

The four parallel data inputs (P0, P1, P2, P3) are D-type inputs. When both S0 and S1 are HIGH, the data appearing on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and

Q3 outputs respectively following the next LOW to HIGH transition of the clock.

The asynchronous Master Reset (MR), when LOW, overrides all other input conditions and forces the Q outputs LOW.

Special logic features of the LS194A design which increase the range of application are described below:

Two mode control inputs (S0, S1) determine the synchronous operation of the device. As shown in the Mode Selection Table, data can be entered and shifted from left to right (shift right, Q0 ≡ Q1, etc.) or right to left (shift left, Q3 ≡ Q2, etc.), or parallel data can be entered loading all four bits of the register simultaneously. When both S0 and S1,are LOW, the existing data is retained in a ªdonothingº mode without restricting the HIGH to LOW clock transition.

D-type serial data inputs (DSR, DSL) are provided on both the first and last stages to allow multistage shift right or shift left data transfers without interfering with parallel load operation.

MODE SELECT Ð TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

MR

S1

S0

DSR

DSL

Pn

Q0

Q1

Q2

Q3

Reset

L

X

X

X

X

X

L

L

L

L

Hold

H

I

I

X

X

X

q0

q1

q2

q3

Shift Left

H

h

I

X

I

X

q1

q2

q3

L

H

h

I

X

h

X

q1

q2

q3

H

Shift Right

H

I

h

I

X

X

L

q0

q1

q2

H

I

h

h

X

X

H

q0

q1

q2

Parallel Load

H

h

h

X

X

Pn

P0

P1

P2

P3

L = LOW Voltage Level

H = HIGH Voltage Level X = Don't Care

I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition

pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition.

FAST AND LS TTL DATA

5-361