3-STATE HEX BUFFERS
These devices are high speed hex buffers with 3-state outputs. They are organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D) paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power Schottky loads when the Enable (E) is LOW.
When the Output Enable (E) is HIGH, the outputs are forced to a high impedance ªoffº state. If the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap.
SN54/74LS365A
SN54/74LS366A
SN54/74LS367A
SN54/74LS368A
3-STATE HEX BUFFERS
LOW POWER SCHOTTKY
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J SUFFIX |
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CERAMIC |
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CASE 620-09 |
16 |
1 |
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N SUFFIX |
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PLASTIC |
16 |
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CASE 648-08 |
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1 |
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D SUFFIX |
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16 |
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SOIC |
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CASE 751B-03 |
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1 |
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ORDERING INFORMATION |
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SN54LSXXXJ |
Ceramic |
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SN74LSXXXN |
Plastic |
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SN74LSXXXD |
SOIC |
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GUARANTEED OPERATING RANGES |
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Symbol |
Parameter |
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Min |
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Typ |
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Max |
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Unit |
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VCC |
Supply Voltage |
54 |
4.5 |
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5.0 |
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5.5 |
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V |
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74 |
4.75 |
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5.0 |
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5.25 |
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TA |
Operating Ambient Temperature Range |
54 |
± 55 |
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25 |
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125 |
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°C |
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74 |
0 |
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25 |
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70 |
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IOH |
Output Current Ð High |
54 |
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± 1.0 |
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mA |
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74 |
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± 2.6 |
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IOL |
Output Current Ð Low |
54 |
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12 |
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mA |
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74 |
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24 |
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FAST AND LS TTL DATA
5-1