MOTOROLA SN74LS251DR2, SN74LS251MEL, SN74LS251ML1, SN74LS251MR1, SN74LS251N Datasheet

SN74LS251

8-Input Multiplexer with 3-State Outputs

The TTL/MSI SN74LS251 is a high speed 8-Input Digital Multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. The LS251 can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.

•Schottky Process for High Speed

•Multifunction Capability

•On-Chip Select Logic Decoding

•Inverting and Non-Inverting 3-State Outputs

•Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Symbol	Parameter	Min	Typ	Max	Unit
VCC	Supply Voltage	4.75	5.0	5.25	V
TA	Operating Ambient	0	25	70	°C
	Temperature Range
IOH	Output Current ± High			± 2.6	mA
IOL	Output Current ± Low			24	mA

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LOW

POWER

SCHOTTKY

16

1

PLASTIC

N SUFFIX

CASE 648

16

1

SOIC

D SUFFIX

CASE 751B

ORDERING INFORMATION

Device	Package	Shipping
SN74LS251N	16 Pin DIP	2000 Units/Box
SN74LS251D	16 Pin	2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
December, 1999 ± Rev. 6		SN74LS251/D

SN74LS251

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC		I4		I5		I6		I7		S0		S1		S2
16		15		14		13		12		11		10		9

9

S2

10

S1

11

S0

7

E1

1

2

3

4

5

6

7

8

I3

I2

I1

I0

Z

0

GND

Z

E

LOADING (Note a)

PIN NAMES

HIGH

LOW

S0 ± S2

Select Inputs

0.5 U.L.

0.25 U.L.

E

0

Output Enable (Active LOW) Inputs

0.5 U.L.

0.25 U.L.

I0 ± I7

Multiplexer Inputs

0.5 U.L.

0.25 U.L.

Z

Multiplexer Output

65 U.L.

15 U.L.

Complementary Multiplexer Output

65 U.L.

15 U.L.

Z

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC DIAGRAM

I0	I1	I2	I3	I4		I5	I6	I7
4	3		2	1	15	14	13	12

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS	5	6
Z		Z

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SN74LS251

FUNCTIONAL DESCRIPTION

The LS251 is a logical implementation of a single pole, 8-position switch with the switch position controlled by the state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input

(EO) is active LOW. When it is activated, the logic function provided at the output is:

Z = EO (I0 S0 S1 S2 + I1 S0 S1 S2 + I2 S0 S1 S2 + I3 S0 S1 S2 + I4 S0 S1 S2 + I5 S0 S1 S2 + I6 S0 S1 S2 + I7 S0 S1 S2).

When the Output Enable is HIGH, both outputs are in the high impedance (high Z) state. This feature allows multiplexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. The Output Enable signals should be designed to ensure there is no overlap in the active LOW portion of the enable voltage.

TRUTH TABLE

E0

S2

S1

S0

I0

I1

I2

I3

I4

I5

I6

I7

Z

Z

H

X

X

X

X

X

X

X

X

X

X

X

(Z)

(Z)

L

L

L

L

L

X

X

X

X X

X

X

H

L

L

L

L

L

H

X

X

X

X X

X

X

L

H

L

L

L

H

X

L

X

X

X X

X

X

H

L

L

L

L

H

X

H

X

X

X X

X

X

L

H

L

L

H

L

X

X

L

X

X X

X

X

H

L

L

L

H

L

X

X

H

X

X X

X

X

L

H

L

L

H

H

X

X

X

L

X X

X

X

H

L

L

L

H

H

X

X

X

H

X X

X

X

L

H

L

H

L

L

X

X

X

X

L X

X

X

H

L

L

H

L

L

X

X

X

X

H X

X

X

L

H

L

H

L

H

X

X

X

X

X L

X

X

H

L

L

H

L

H

X

X

X

X

X H

X

X

L

H

L

H

H

L

X

X

X

X

X X

L

X

H

L

L

H

H

L

X

X

X

X

X X

H

X

L

H

L

H

H

H

X

X

X

X

X X

X

L

H

L

L

H

H

H

X

X

X

X

X X

X

H

L

H

H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care

(Z) = High impedance (Off)

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