MOTOROLA SN74LS298D, SN74LS298DR2, SN74LS298ML1, SN74LS298ML2, SN74LS298N Datasheet

SN74LS298

Quad 2-Input Multiplexer with Storage

The SN74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the Clock input.

The LS298 is fabricated with the Schottky barrier process for high speed and is completely compatible with all ON Semiconductor TTL families.

•Select From Two Data Sources

•Fully Edge-Triggered Operation

•Typical Power Dissipation of 65 mW

•Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Symbol	Parameter	Min	Typ	Max	Unit
VCC	Supply Voltage	4.75	5.0	5.25	V
TA	Operating Ambient	0	25	70	°C
	Temperature Range
IOH	Output Current ± High			± 0.4	mA
IOL	Output Current ± Low			8.0	mA

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LOW

POWER

SCHOTTKY

16

1

PLASTIC

N SUFFIX

CASE 648

16

1

SOIC

D SUFFIX

CASE 751B

ORDERING INFORMATION

Device	Package	Shipping
SN74LS298N	16 Pin DIP	2000 Units/Box
SN74LS298D	16 Pin	2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
December, 1999 ± Rev. 6		SN74LS298/D

SN74LS298

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Qa

Qb

Qc

Qd

CP

S

I0c

16

15

14

13

12

11

10

9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1

2

3

4

5

6

7

8

I1b

I1a

I0a

I0b

I1c

I1d

I0d

GND

LOADING (Note a)

PIN NAMES

HIGH

LOW

S

Common Select Input

0.5 U.L.

0.25 U.L.

Clock (Active LOW Going Edge) Input

0.5 U.L.

0.25 U.L.

CP

I0a ± I0d

Data Inputs from Source 0

0.5 U.L.

0.25 U.L.

I1a ± I1d

Data Inputs from Source 1

0.5 U.L.

0.25 U.L.

Qa ± Qd

Register Outputs

10 U.L.

5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL

3		2		4		1		9		5		7		6
	I0a		I1a	I0b I1b				I0c		I1c		I0d		I1d

10S

11 CP

Qa		Qb		Qc		Qd
15		14		13		12
		VCC = PIN 16
		GND = PIN 8

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2

SN74LS298

LOGIC OR BLOCK DIAGRAM

I1a	I0a	I1b	I0b	I1c	I0c	I1d	I0d
2	3	1	4	5	9	6	7

S

10

CP

11

R	R	R	R
CP	CP	CP	CP
S Qa	S Qb	S Qc	S Qd
15	14	13	12

VCC = PIN 16	Qa
GND = PIN 8
= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS298 is a high speed Quad 2-Port Register. It selects four bits of data from two sources (ports)under the control of a Common Select Input (S). The selected data is transferred to the 4-bit output register synchronous with the HIGH to LOW transition of the Clock input (CP). The 4-bit

Qb

Qc

Qd

output register is fully edge-triggered. The Data inputs (I) and Select input (S) must be stable only one setup time prior to the HIGH to LOW transition of the clock for predictable operation.

TRUTH TABLE

	INPUTS		OUTPUT
S	I0	I1	Q
I	I	X	L
I	h	X	H
h	X	I	L
h	X	h	H

L = LOW Voltage Level

H = HIGH Voltage Level X = Don't Care

I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.

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3