MOTOROLA SN74LS123M, SN74LS123MEL, SN74LS123ML1, SN74LS123ML2, SN74LS123MR1 Datasheet

SN74LS122 SN74LS123

Retriggerable Monostable

Multivibrators

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.

•Overriding Clear Terminates Output Pulse

•Compensated for VCC and Temperature Variations

•DC Triggered from Active-High or Active-Low Gated Logic Inputs

•Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle

•Internal Timing Resistors on LS122

GUARANTEED OPERATING RANGES

Symbol	Parameter	Min	Typ	Max	Unit
VCC	Supply Voltage	4.75	5.0	5.25	V
TA	Operating Ambient	0	25	70	°C
	Temperature Range
IOH	Output Current ± High			± 0.4	mA
IOL	Output Current ± Low			8.0	mA
Rext	External Timing Resistance	5.0		260	kW
Cext	External Capacitance		No Restriction
Rext/Cext	Wiring Capacitance at			50	pF
	Rext/Cext Terminal

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LOW POWER SCHOTTKY

14

1

PLASTIC

N SUFFIX CASE 646

14

1

SOIC

D SUFFIX

CASE 751A

16

1

PLASTIC

N SUFFIX CASE 648

16

1

SOIC

D SUFFIX

CASE 751B

ORDERING INFORMATION

Device	Package	Shipping
SN74LS122N	14 Pin DIP	2000 Units/Box
SN74LS122D	14 Pin	2500/Tape & Reel
SN74LS123N	16 Pin DIP	2000 Units/Box
SN74LS123D	16 Pin	2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
December, 1999 ± Rev. 6		SN74LS122/D

SN74LS122 SN74LS123

	SN74LS123 (TOP VIEW)
	(SEE NOTES 1 THRU 4)
VCC	1 Rext/	1	1Q	2Q	2		2A
	Cext	Cext			CLR	2B
16	15	14	13	12	11	10	9
		Q			CLR
					Q
		CLR Q			Q
1	2	3	4	5	6	7	8
1A	1B	1	1Q	2Q	2	2	GND
		CLR			Cext	Rext/
						Cext

SN74LS122 (TOP VIEW) (SEE NOTES 1 THRU 4)

VCC	Rext/	NC	Cext	NC	Rint	Q
	Cext
14	13	12	11	10	9	8
				Rint
					Q
				CLR	Q
1	2	3	4	5	6	7
A1	A2	B1	B2	CLR	Q	GND

NC Ð NO INTERNAL CONNECTION.

NOTES:

1.An external timing capacitor may be connected between Cext and Rext/Cext (positive).

2.To use the internal timing resistor of the LS122, connect Rint to VCC.

3.For improved pulse width accuracy connect an external resistor between Rext/Cext and VCC with Rint open-circuited.

4.To obtain variable pulse widths, connect an external variable resistance between Rint/Cext and VCC.

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SN74LS122 SN74LS123

LS122 FUNCTIONAL TABLE

INPUTS

OUTPUTS

CLEAR

A1

A2

B1

B2

Q

Q

L

X

X

X

X

L

H

X

H

H

X

X

L

H

X

X

X

L

X

L

H

X

X

X

X

L

L

H

H

L

X

↑

H

H

L

X

H

↑

H

X

L

↑

H

H

X

L

H

↑

H

H

↓

H

H

H

↓

↓

H

H

H

↓

H

H

H

↑

L

X

H

H

↑

X

L

H

H

LS123 FUNCTIONAL TABLE

INPUTS

OUTPUTS

CLEAR

A

B

Q

Q

L

X

X

L

H

X

H

X

L

H

X

X

L

L

H

H

L

↑

H

↓

H

↑

L

H

TYPICAL APPLICATION DATA

The output pulse tW is a function of the external

components, Cext and Rext or Cext and Rint on the LS122. For values of Cext ≥ 1000 pF, the output pulse at VCC = 5.0 V and VRC = 5.0 V (see Figures 1, 2, and 3) is given by

tW = K Rext Cext where K is nominally 0.45

If Cext is on pF and Rext is in kΩ then tW is in nanoseconds. The Cext terminal of the LS122 and LS123 is an internal connection to ground, however for the best system

performance Cext should be hard-wired to ground.

Care should be taken to keep Rext and Cext as close to the monostable as possible with a minimum amount of

inductance between the Rext/Cext junction and the Rext/Cext pin. Good groundplane and adequate bypassing should be

designed into the system for optimum performance to ensure that no false triggering occurs.

It should be noted that the Cext pin is internally connected to ground on the LS122 and LS123, but not on the LS221. Therefore, if Cext is hard-wired externally to ground, substitution of a LS221 onto a LS123 socket will cause the LS221 to become non-functional.

The switching diode is not needed for electrolytic capacitance application and should not be used on the LS122 and LS123.

To find the value of K for Cext ≥ 1000 pF, refer to Figure 4. Variations on VCC or VRC can cause the value of K to

change, as can the temperature of the LS123, LS122.

Figures 5 and 6 show the behavior of the circuit shown in Figures 1 and 2 if separate power supplies are used for VCC

and VRC. If VCC is tied to VRC, Figure 7 shows how K will vary with VCC and temperature. Remember, the changes in

Rext and Cext with temperature are not calculated and included in the graph.

As long as Cext ≥ 1000 pF and 5K ≤ Rext ≤ 260K, the change in K with respect to Rext is negligible.

If Cext ≤ 1000 pF the graph shown on Figure 8 can be used to determine the output pulse width. Figure 9 shows how K

will change for Cext ≤ 1000 pF if VCC and VRC are connected to the same power supply. The pulse width tW in

nanoseconds is approximated by

tW = 6 + 0.05 Cext (pF) + 0.45 Rext (kΩ) Cext + 11.6 Rext In order to trim the output pulse width, it is necessary to

include a variable resistor between VCC and the Rext/Cext pin or between VCC and the Rext pin of the LS122. Figure 10, 11, and 12 show how this can be done. Rext remote should be kept as close to the monostable as possible.

Retriggering of the part, as shown in Figure 3, must not occur before Cext is discharged or the retrigger pulse will not have any effect. The discharge time of Cext in nanoseconds is guaranteed to be less than 0.22 Cext (pF) and is typically

0.05 Cext (pF).

For the smallest possible deviation in output pulse widths from various devices, it is suggested that Cext be kept ≥ 1000 pF.

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SN74LS122 SN74LS123

WAVEFORMS

RETRIGGER
PULSE	(See Application Data)

B INPUT

Q OUTPUT

tW OUTPUT WITHOUT RETRIGGER

EXTENDING PULSE WIDTH

B INPUT

CLEAR INPUT

CLEAR PULSE

OUTPUT WITHOUT CLEAR PULSE

Q OUTPUT

OVERRIDING THE OUTPUT PULSE

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