MOTOROLA SN74LS259D, SN74LS259DR2, SN74LS259M, SN74LS259MEL, SN74LS259ML1 Datasheet
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SN74LS259
8-Bit Addressable Latch
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1-of-8 decoder and demultiplexer with active HIGH outputs. The device also incorporates an active LOW common Clear for resetting all latches, as well as, an active LOW Enable.
•Serial-to-Parallel Conversion
•Eight Bits of Storage With Output of Each Bit Available
•Random (Addressable) Data Entry
•Active High Demultiplexing or Decoding Capability
•Easily Expandable
•Common Clear
GUARANTEED OPERATING RANGES
Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
4.75 |
5.0 |
5.25 |
V |
TA |
Operating Ambient |
0 |
25 |
70 |
°C |
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Temperature Range |
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IOH |
Output Current ± High |
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± 0.4 |
mA |
IOL |
Output Current ± Low |
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8.0 |
mA |
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LOW
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CASE 648
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CASE 751B
ORDERING INFORMATION
Device |
Package |
Shipping |
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SN74LS259N |
16 Pin DIP |
2000 Units/Box |
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SN74LS259D |
16 Pin |
2500/Tape & Reel |
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Semiconductor Components Industries, LLC, 1999 |
1 |
Publication Order Number: |
December, 1999 ± Rev. 6 |
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SN74LS259/D |
SN74LS259
CONNECTION DIAGRAM DIP (TOP VIEW)
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VCC |
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C |
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E |
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D |
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Q7 |
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Q6 |
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Q5 |
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Q4 |
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16 |
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15 |
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14 |
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13 |
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12 |
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11 |
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10 |
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9 |
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7 |
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8 |
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Ao |
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A1 |
A2 |
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Q0 |
Q1 |
Q2 |
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Q3 |
GND |
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LOADING (Note a) |
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PIN NAMES |
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HIGH |
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LOW |
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A0, A1, A2 |
Address Inputs |
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0.5 U.L. |
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0.25 U.L. |
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D |
Data Input |
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0.5 U.L. |
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0.25 U.L. |
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Enable (Active LOW) Input |
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1.0 U.L. |
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0.5 U.L. |
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E |
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C |
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Clear (Active LOW) Input |
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0.5 U.L. |
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0.25 U.L. |
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Q0 ± Q7 |
Parallel Latch Outputs |
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10 U.L. |
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5 U.L. |
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NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
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SN74LS259
LOGIC DIAGRAM
E |
D |
A0 |
A1 |
A2 |
C |
14 |
13 |
1 |
2 |
3 |
15 |
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VCC = PIN 16 |
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GND = PIN 8 |
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= PIN NUMBERS |
4 |
Q0
5 |
6 |
7 |
Q1 |
Q2 |
Q3 |
9 |
Q4 |
10 |
Q5 |
11 |
12 |
Q6 |
Q7 |
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in the mode selection table. In the addressable latch mode, data on the Data line (D) is written into the addressed latch.The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the addressed output will follow the state of the D input with all
MODE SELECTION
other inputs in the LOW state. In the clear mode all outputs are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch, changing more then one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
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E |
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C |
MODE |
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L |
H |
Addressable Latch |
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H |
H |
Memory |
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L |
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L |
Active HIGH Eight-Channel |
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Demultiplexer |
H |
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L |
Clear |
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X = Don't Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
QN±1 = Previous Output State
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C E D A0 |
A1 |
A2 |
Q0 |
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Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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MODE |
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L |
H |
X |
X |
X |
X |
L |
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L |
L |
L |
L |
L |
L |
L |
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Clear |
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L |
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L |
L |
L |
L |
L |
L |
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L |
L |
L |
L |
L |
L |
L |
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Demultiplex |
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L |
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L H L |
L |
L |
H |
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L |
L |
L |
L |
L |
L |
L |
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L |
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L L H |
L |
L |
L |
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L |
L |
L |
L |
L |
L |
L |
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L |
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L H H L |
L |
L |
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H |
L |
L |
L |
L |
L |
L |
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• • |
• |
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• |
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• |
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• • |
• |
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• |
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• |
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• • |
• |
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• |
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• |
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• • |
• |
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• |
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• |
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• • |
• |
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• |
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• |
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L |
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L H H H H |
L |
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L |
L |
L |
L |
L |
L |
H |
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H H X |
X |
X |
X |
QN±1 |
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Memory |
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H |
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I |
I |
L |
L |
L |
L |
QN±1 |
QN±1 |
QN±1 |
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Addressable |
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H |
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L |
H |
L |
L |
L |
H |
QN±1 |
QN±1 |
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Latch |
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H |
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L |
L |
H |
L |
L |
QN±1 |
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L |
QN±1 |
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H |
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L H |
H |
L |
L |
QN±1 |
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H |
QN±1 |
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• |
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• • |
• |
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• • |
• |
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• |
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• • |
• |
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• |
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• |
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• • |
• |
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• |
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• • |
• |
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• |
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H |
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L |
L |
H |
H |
H |
QN±1 |
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QN±1 |
L |
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H |
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L H |
H |
H |
H |
QN±1 |
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QN±1 |
H |
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