MOTOROLA SN74LS253ML2, SN74LS253N, SN74LS253D, SN74LS253DR2, SN74LS253M Datasheet

SN74LS253

Dual 4-Input Multiplexer with 3-State Outputs

The LSTTL / MSI SN74LS253 is a Dual 4-Input Multiplexer with 3-state outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families.

•Schottky Process for High Speed

•Multifunction Capability

•Non-Inverting 3-State Outputs

•Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Symbol	Parameter	Min	Typ	Max	Unit
VCC	Supply Voltage	4.75	5.0	5.25	V
TA	Operating Ambient	0	25	70	°C
	Temperature Range
IOH	Output Current ± High			± 2.6	mA
IOL	Output Current ± Low			24	mA

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LOW

POWER

SCHOTTKY

16

1

PLASTIC

N SUFFIX

CASE 648

16

1

SOIC

D SUFFIX

CASE 751B

ORDERING INFORMATION

Device	Package	Shipping
SN74LS253N	16 Pin DIP	2000 Units/Box
SN74LS253D	16 Pin	2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999	1	Publication Order Number:
December, 1999 ± Rev. 6		SN74LS253/D

SN74LS253

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC

E0b

S0

I3b

I2b

I1b

I0b

Zb

16

15

14

13

12

11

10

9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1

2

3

4

5

6

7

8

0a

S1

I3a

I2a

I1a

I0a

Za

GND

E

LOADING (Note a)

PIN NAMES

HIGH

LOW

S0, S1

Common Select Inputs

0.5 U.L.

0.25 U.L.

Multiplexer A

E

0a

Output Enable (Active LOW) Input

0.5 U.L.

0.25 U.L.

I0a ± I3a

Multiplexer Inputs

0.5 U.L.

0.25 U.L.

Za

Multiplexer Output

65 U.L.

15 U.L.

Multiplexer B

0b

Output Enable (Active LOW) Input

0.5 U.L.

0.25 U.L.

E

I0b ± I3b

Multiplexer Inputs

0.5 U.L.

0.25 U.L.

Zb

Multiplexer Output

65 U.L.

15 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOGIC SYMBOL

	1	6	5	4	3	10	11	12 13	15
14	E0a	I0a	I1a	I2a	I3a	I0b	I1b	I2b I3b E0b
	S0
2	S1		Za				Zb
				7			9
				VCC = PIN 16
				GND = PIN 8

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						SN74LS253
						LOGIC DIAGRAM
E0b	I3b		I2b	I1b	I0b	S0	S1	I3a	I2a	I1a	I0a	E0a
	15	13	12	11	10	14	2	3	4	5	6	1

Zb 9	VCC = PIN 16
	GND = PIN 8	Za 7
	= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS253 contains two identical 4-Input Multiplexers with 3-state outputs. They select two bits from four sources selected by common select inputs (S0, S1). The 4-input

multiplexers have individual Output Enable (E0a, E0b) inputs which when HIGH, forces the outputs to a high impedance (high Z) state.

The LS253 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown below:

Za = E0a (I0a S1 S0 + I1a S1 S0 I2a S1 S0 + I3a S1 S0) Zb = E0b (I0b S1 S0 + I1b S1 S0 I2b S1 S0 + I3b S1 S0)

If the outputs of 3-state devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3-state devices whose outputs are tied together are designed so that there is no overlap.

TRUTH TABLE

SELECT			DATA INPUTS			OUTPUT			OUTPUT
INPUTS						ENABLE
S0	S1	I0	I1	I2	I3			0	Z
							E
X	X	X	X	X	X		H		(Z)
L	L	L	X	X	X		L		L
L	L	H	X	X	X		L		H
H	L	X	L	X	X		L		L
H	L	X	H	X	X		L		H
L	H	X	X	L	X		L		L
L	H	X	X	H	X		L		H
H	H	X	X	X	L		L		L
H	H	X	X	X	H		L		H

H = HIGH Level

L = LOW Level

X = Irrelevant

(Z) = High Impedance (off)

Address inputs S0 and S1 are common to both sections.

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