QUAD D FLIP-FLOP
The LSTTL /MSI SN54 /74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW.
The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.
•Edge-Triggered D-Type Inputs
•Buffered-Positive Edge-Triggered Clock
•Clock to Output Delays of 30 ns
•Asynchronous Common Reset
•True and Complement Output
•Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC |
|
Q3 |
Q3 |
|
D3 |
|
D2 |
|
Q2 |
|
Q2 |
|
CP |
|||
|
16 |
|
15 |
|
14 |
|
13 |
|
12 |
|
11 |
|
10 |
|
9 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NOTE: |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
The Flatpak version |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
has the same pinouts |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(Connection Diagram) as |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
the Dual In-Line Package. |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
|
2 |
|
3 |
|
4 |
|
5 |
|
6 |
|
7 |
|
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MR |
Q0 |
|
Q0 |
|
D0 |
|
D1 |
Q1 |
|
Q1 |
GND |
|
|
|
|
|
|||||
PIN NAMES |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LOADING (Note a) |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HIGH |
LOW |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
D0 ± D3 |
|
Data Inputs |
|
|
|
|
|
|
|
|
|
0.5 |
U.L. |
0.25 |
U.L. |
|||||||
CP |
|
Clock (Active HIGH Going Edge) Input |
|
0.5 U.L. |
0.25 |
U.L. |
||||||||||||||||
MR |
|
Master Reset (Active LOW) Input |
|
|
0.5 |
U.L. |
0.25 |
U.L. |
||||||||||||||
Q0 ± Q3 |
|
True Outputs (Note b) |
|
|
|
|
|
10 |
U.L. |
5 (2.5) |
U.L. |
|||||||||||
Q0 ± Q3 |
|
Complemented Outputs (Note b) |
|
|
10 |
U.L. |
5 (2.5) |
U.L. |
||||||||||||||
NOTES:
a.1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b.The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b.Temperature Ranges.
LOGIC DIAGRAM
MR CP |
D3 |
|
|
D2 |
|
|
D1 |
|
|
D0 |
|
|
|
1 |
9 |
13 |
|
|
12 |
|
|
5 |
|
|
4 |
|
|
|
|
D |
Q |
|
D |
Q |
|
D |
Q |
|
D |
Q |
|
|
|
CP Q |
|
CP Q |
|
CP Q |
|
CP Q |
|
||||
|
|
CD |
|
CD |
|
CD |
|
CD |
|
||||
|
|
|
14 |
15 |
|
11 |
10 |
|
6 |
7 |
|
3 |
2 |
VCC |
= |
PIN |
16 |
Q3 Q3 |
|
|
Q2 Q2 |
|
|
Q1Q1 |
|
|
Q0Q0 |
GND |
= |
PIN |
8 |
|
|
|
|
|
|
||||
= PIN NUMBERS
SN54/74LS175
QUAD D FLIP-FLOP
LOW POWER SCHOTTKY
|
|
|
J SUFFIX |
|
|
|
CERAMIC |
|
|
|
CASE 620-09 |
16 |
1 |
|
|
|
|
|
|
|
|
|
N SUFFIX |
|
|
|
PLASTIC |
16 |
|
|
CASE 648-08 |
|
|
|
|
|
1 |
|
|
|
|
|
D SUFFIX |
|
16 |
|
SOIC |
|
|
CASE 751B-03 |
|
|
|
1 |
|
|
|
|
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
|
|
4 |
5 |
12 |
13 |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D0 |
D1 |
D2 |
D3 |
||||
9 |
|
|
CP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
1 
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
3 2 6 7 11 10 14 15
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-327
SN54/74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to follow. A
LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs.
The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H) |
Outputs (t = n+1) Note 1 |
|
|
|
|
D |
Q |
Q |
|
|
|
L |
L |
H |
H |
H |
L |
|
|
|
Note 1: t = n + 1 indicates conditions after next clock.
GUARANTEED OPERATING RANGES
Symbol |
Parameter |
|
Min |
Typ |
Max |
Unit |
|
|
|
|
|
|
|
VCC |
Supply Voltage |
54 |
4.5 |
5.0 |
5.5 |
V |
|
|
74 |
4.75 |
5.0 |
5.25 |
|
|
|
|
|
|
|
|
TA |
Operating Ambient Temperature Range |
54 |
± 55 |
25 |
125 |
°C |
|
|
74 |
0 |
25 |
70 |
|
|
|
|
|
|
|
|
IOH |
Output Current Ð High |
54, 74 |
|
|
± 0.4 |
mA |
IOL |
Output Current Ð Low |
54 |
|
|
4.0 |
mA |
|
|
74 |
|
|
8.0 |
|
|
|
|
|
|
|
|
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
|
|
|
|
Limits |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
|
Test Conditions |
||
|
|
|
|
|
|
|
|
|
|
VIH |
Input HIGH Voltage |
2.0 |
|
|
V |
Guaranteed Input HIGH Voltage for |
|||
|
|
All Inputs |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VIL |
Input LOW Voltage |
54 |
|
|
0.7 |
V |
Guaranteed Input LOW Voltage for |
||
74 |
|
|
0.8 |
All Inputs |
|
|
|||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
VIK |
Input Clamp Diode Voltage |
|
± 0.65 |
± 1.5 |
V |
VCC = MIN, IIN = ±18 mA |
|||
VOH |
Output HIGH Voltage |
54 |
2.5 |
3.5 |
|
V |
VCC = MIN, IOH = MAX, VIN = VIH |
||
74 |
2.7 |
3.5 |
|
V |
or VIL per Truth Table |
||||
|
|
|
|||||||
|
|
54, 74 |
|
0.25 |
0.4 |
V |
I = 4.0 mA |
|
VCC = VCC MIN, |
VOL |
Output LOW Voltage |
|
|
|
|
|
OL |
|
VIN = VIL or VIH |
74 |
|
0.35 |
0.5 |
V |
IOL = 8.0 mA |
|
|||
|
|
|
|
per Truth Table |
|||||
IIH |
Input HIGH Current |
|
|
20 |
μA |
VCC = MAX, VIN = 2.7 V |
|||
|
|
0.1 |
mA |
VCC = MAX, VIN = 7.0 V |
|||||
|
|
|
|
|
|||||
IIL |
Input LOW Current |
|
|
± 0.4 |
mA |
VCC = MAX, VIN = 0.4 V |
|||
IOS |
Short Circuit Current (Note 1) |
± 20 |
|
± 100 |
mA |
VCC = MAX |
|
|
|
ICC |
Power Supply Current |
|
|
18 |
mA |
VCC = MAX |
|
|
|
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-328
Loading...