OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
The SN54/74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state.
The SN54/74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54/74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.
•Eight Latches in a Single Package
•3-State Outputs for Bus Interfacing
•Hysteresis on Latch Enable
•Edge-Triggered D-Type Inputs
•Buffered Positive Edge-Triggered Clock
•Hysteresis on Clock Input to Improve Noise Margin
•Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES |
LOADING (Note a) |
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HIGH |
LOW |
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D0 ± D7 |
Data Inputs |
0.5 |
U.L. |
0.25 |
U.L. |
LE |
Latch Enable (Active HIGH) Input |
0.5 |
U.L. |
0.25 |
U.L. |
CP |
Clock (Active HIGH going edge) Input |
0.5 |
U.L. |
0.25 |
U.L. |
OE |
Output Enable (Active LOW) Input |
0.5 |
U.L. |
0.25 |
U.L. |
O0 ± O7 |
Outputs (Note b) |
65 (25) |
U.L. |
15 (7.5) |
U.L. |
NOTES:
a)1 TTL Units Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b)The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial
(74)Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges.
SN54/74LS373
SN54/74LS374
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
LOW POWER SCHOTTKY
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J SUFFIX |
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CERAMIC |
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20 |
CASE 732-03 |
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N SUFFIX |
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PLASTIC |
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20 |
CASE 738-03 |
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1 |
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DW SUFFIX |
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SOIC |
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CASE 751D-03 |
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1 |
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
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CONNECTION DIAGRAM DIP (TOP VIEW) |
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SN54 / 74LS374 |
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SN54 / 74LS373 |
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VCC O7 |
D7 |
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D6 |
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O6 |
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O5 |
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D5 |
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D4 |
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O4 |
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LE |
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V |
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O |
7 |
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D D |
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O |
6 |
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O |
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D |
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D |
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O |
4 |
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CP |
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CC |
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7 |
6 |
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5 |
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4 |
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20 |
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20 |
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NOTE: |
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OE |
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O0 |
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D0 |
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D1 |
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O1 |
O2 |
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D2 |
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D3 |
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O3 |
GND |
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The Flatpak version |
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OE |
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O0 |
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D0 |
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D1 |
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O1 |
O2 |
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D2 |
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D3 |
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O3 |
GND |
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has the same pinouts (Connection Diagram) as the Dual In-Line Package.
FAST AND LS TTL DATA
5-521
SN54/74LS373 •SN54/74LS374
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TRUTH TABLE |
LS373 |
LS374 |
Dn |
LE |
OE |
On |
H |
H |
L |
H |
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L |
H |
L |
L |
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X |
L |
L |
Q0 |
X |
X |
H |
Z* |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Dn |
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LE |
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OE |
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On |
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H |
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L |
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H |
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L |
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L |
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L |
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X |
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X |
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H |
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Z* |
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* Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE). |
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LOGIC DIAGRAMS |
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SN54LS / 74LS373 |
3 |
4 |
7 |
8 |
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13 |
14 |
17 |
18 |
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VCC = PIN 20 |
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D0 |
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D1 |
D2 |
D3 |
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D4 |
D5 |
D6 |
D7 |
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GND |
= |
PIN |
10 |
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D |
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D |
D |
D |
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D |
D |
D |
D |
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= PIN |
NUMBERS |
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LATCH |
Q |
Q |
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Q |
Q |
Q |
Q |
Q |
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Q |
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ENABLE |
G |
G |
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G |
G |
G |
G |
G |
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G |
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11 |
LE |
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1 |
OE |
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O0 |
O1 |
O2 |
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O3 |
O4 |
O5 |
O6 |
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O7 |
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2 |
5 |
6 |
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12 |
15 |
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19 |
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SN54LS / 74LS374 |
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7 |
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13 |
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17 |
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18 |
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11 |
D0 |
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D1 |
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D2 |
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D3 |
D4 |
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D5 |
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D6 |
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D7 |
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CP |
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CP D |
CP |
D |
CP |
D |
CP |
D |
CP D |
CP |
D |
CP |
D |
CP |
D |
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Q Q |
Q Q |
Q Q |
Q Q |
Q Q |
Q Q |
Q Q |
Q Q |
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OE |
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1 |
O0 |
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O1 |
O2 |
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O3 |
O4 |
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O5 |
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O6 |
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O7 |
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2 |
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5 |
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9 |
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15 |
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GUARANTEED OPERATING RANGES
Symbol |
Parameter |
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Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
54 |
4.5 |
5.0 |
5.5 |
V |
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74 |
4.75 |
5.0 |
5.25 |
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TA |
Operating Ambient Temperature Range |
54 |
± 55 |
25 |
125 |
°C |
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74 |
0 |
25 |
70 |
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IOH |
Output Current Ð High |
54 |
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± 1.0 |
mA |
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74 |
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± 2.6 |
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IOL |
Output Current Ð Low |
54 |
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12 |
mA |
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74 |
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24 |
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FAST AND LS TTL DATA
5-522
SN54/74LS373 •SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
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Limits |
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Symbol |
Parameter |
Min |
Typ |
Max |
Unit |
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Test Conditions |
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VIH |
Input HIGH Voltage |
2.0 |
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V |
Guaranteed Input HIGH Voltage for |
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All Inputs |
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VIL |
Input LOW Voltage |
54 |
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0.7 |
V |
Guaranteed Input LOW Voltage for |
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0.8 |
All Inputs |
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VIK |
Input Clamp Diode Voltage |
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± 0.65 |
± 1.5 |
V |
VCC = MIN, IIN = ±18 mA |
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VOH |
Output HIGH Voltage |
54 |
2.4 |
3.4 |
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V |
VCC = MIN, IOH = MAX, VIN = VIH |
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74 |
2.4 |
3.1 |
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V |
or VIL per Truth Table |
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54, 74 |
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0.25 |
0.4 |
V |
I = 12 mA |
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VCC = VCC MIN, |
VOL |
Output LOW Voltage |
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OL |
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VIN = VIL or VIH |
74 |
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0.35 |
0.5 |
V |
IOL = 24 mA |
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per Truth Table |
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IOZH |
Output Off Current HIGH |
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20 |
μA |
VCC = MAX, VOUT = 2.7 V |
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IOZL |
Output Off Current LOW |
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± 20 |
μA |
VCC = MAX, VOUT = 0.4 V |
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IIH |
Input HIGH Current |
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20 |
μA |
VCC = MAX, VIN = 2.7 V |
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0.1 |
mA |
VCC = MAX, VIN = 7.0 V |
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IIL |
Input LOW Current |
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± 0.4 |
mA |
VCC = MAX, VIN = 0.4 V |
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IOS |
Short Circuit Current (Note 1) |
± 30 |
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± 130 |
mA |
VCC = MAX |
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ICC |
Power Supply Current |
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40 |
mA |
VCC = MAX |
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Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
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Limits |
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LS373 |
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LS374 |
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Symbol |
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Parameter |
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Unit |
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Test Conditions |
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Min |
Typ |
Max |
Min |
Typ |
Max |
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fMAX |
Maximum Clock Frequency |
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35 |
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50 |
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MHz |
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tPLH |
Propagation Delay, |
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12 |
18 |
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ns |
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tPHL |
Data to Output |
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12 |
18 |
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CL = 45 pF, |
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tPLH |
Clock or Enable |
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20 |
30 |
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15 |
28 |
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ns |
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RL = 667 Ω |
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tPHL |
to Output |
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18 |
30 |
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19 |
28 |
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tPZH |
Output Enable Time |
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15 |
28 |
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20 |
28 |
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ns |
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tPZL |
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25 |
36 |
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21 |
28 |
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tPHZ |
Output Disable Time |
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12 |
20 |
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12 |
20 |
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CL = 5.0 pF |
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tPLZ |
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15 |
25 |
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15 |
25 |
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AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) |
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Limits |
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LS373 |
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LS374 |
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Symbol |
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Parameter |
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Unit |
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Min |
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Max |
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Min |
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Max |
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tW |
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Clock Pulse Width |
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15 |
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15 |
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ns |
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ts |
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Setup Time |
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5.0 |
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20 |
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ns |
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th |
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Hold Time |
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20 |
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0 |
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ns |
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DEFINITION OF TERMS
SETUP TIME (ts) Ð is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs.
HOLD TIME (th) Ð is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.
FAST AND LS TTL DATA
5-523
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