SN74LS165
8-Bit Parallel-to-Serial
Shift Register
The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable.
GUARANTEED OPERATING RANGES
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Min |
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Max |
Unit |
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VCC |
Supply Voltage |
4.75 |
5.0 |
5.25 |
V |
TA |
Operating Ambient |
0 |
25 |
70 |
°C |
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Temperature Range |
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IOH |
Output Current ± High |
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± 0.4 |
mA |
IOL |
Output Current ± Low |
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8.0 |
mA |
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LOW
POWER
SCHOTTKY
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device |
Package |
Shipping |
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SN74LS165N |
16 Pin DIP |
2000 Units/Box |
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SN74LS165D |
16 Pin |
2500/Tape & Reel |
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Semiconductor Components Industries, LLC, 1999 |
1 |
Publication Order Number: |
December, 1999 ± Rev. 6 |
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SN74LS165/D |
SN74LS165
CONNECTION DIAGRAM DIP (TOP VIEW)
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VCC |
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CP2 |
P3 |
P2 |
P1 |
P0 |
DS |
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Q7 |
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16 |
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15 |
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NOTE: |
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The Flatpak version has the same |
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pinouts (Connection Diagram) as |
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the Dual In-Line Package. |
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CP1 |
P4 |
P5 |
P6 |
P7 |
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GND |
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PL |
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Q7 |
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LOADING (Note a) |
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PIN NAMES |
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HIGH |
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LOW |
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CP1, CP2 |
Clock (LOW±to±HIGH Going Edge) Inputs |
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0.5 U.L. |
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0.25 U.L. |
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DS |
Serial Data Input |
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0.5 U.L. |
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0.25 U.L. |
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Asynchronous Parallel Load (Active LOW) Input |
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1.5 U.L. |
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0.75 U.L. |
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PL |
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P0 ± P7 |
Parallel Data Inputs |
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0.5 U.L. |
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0.25 U.L. |
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Q7 |
Serial Output from Last State |
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10 U.L. |
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5 U.L. |
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Q |
7 |
Complementary Output |
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10 U.L. |
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5 U.L. |
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NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
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LOGIC SYMBOL
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PL P0 P1 P2 P3 P4 P5 P6 P7 |
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DS |
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Q7 |
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CP |
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Q |
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VCC = PIN 16
GND = PIN 8
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SN74LS165 |
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LOGIC DIAGRAM |
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P0 |
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P1 |
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P2 |
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P3 |
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P4 |
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P5 |
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P6 |
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P7 |
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DS |
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2 |
CP1 |
PRESET |
PRESET |
PRESET |
PRESET |
PRESET |
PRESET |
PRESET |
PRESET |
9 |
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S Q0 |
S Q1 |
S Q2 |
S Q3 |
S Q4 |
S Q5 |
S Q6 |
S Q7 |
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CP2 |
CP |
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CP |
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CP |
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CP |
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CP |
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CP |
CP |
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CP |
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R |
C |
Q |
R |
C |
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R |
C |
Q2 |
R |
Q |
R |
C |
Q |
R |
Q |
R |
C |
Q |
R |
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Q |
7 |
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L |
0 |
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L |
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1 |
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L |
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C 3 |
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L |
4 |
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C 5 |
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L |
6 |
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L |
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L |
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1 |
PL |
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VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock.
TRUTH TABLE
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CP |
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CONTENTS |
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RESPONSE |
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PL |
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1 |
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2 |
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
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Q5 |
Q6 |
Q7 |
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L |
X |
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X |
P0 |
P1 |
P2 |
P3 |
P4 |
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P5 |
P6 |
P7 |
Parallel Entry |
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H |
L |
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DS |
Q0 |
Q1 |
Q2 |
Q3 |
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Q4 |
Q5 |
Q6 |
Right Shift |
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H |
H |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
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Q5 |
Q6 |
Q7 |
No Change |
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H |
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L |
DS |
Q0 |
Q1 |
Q2 |
Q3 |
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Q4 |
Q5 |
Q6 |
Right Shift |
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H |
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H |
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
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Q5 |
Q6 |
Q7 |
No Change |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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