Motorola SN54LS390J, SN74LS390D, SN74LS390N Datasheet

DUAL DECADE COUNTER; DUAL 4-STAGE

BINARY COUNTER

The SN54/74LS390 and SN54/74LS393 each contain a pair of high-speed 4-stage ripple counters. Each half of the LS390 is partitioned into a divide-by-two section and a divide-by five section, with a separate clock input for each section. The two sections can be connected to count in the 8.4.2.1 BCD code or they can count in a biquinary sequence to provide a square wave (50% duty cycle) at the final output.

Each half of the LS393 operates as a Modulo-16 binary divider, with the last three stages triggered in a ripple fashion. In both the LS390 and the LS393, the flip-flops are triggered by a HIGH-to-LOW transition of their CP inputs. Each half of each circuit type has a Master Reset input which responds to a HIGH signal by forcing all four outputs to the LOW state.

•Dual Versions of LS290 and LS293

•LS390 has Separate Clocks Allowing 2, 2.5, 5

•Individual Asynchronous Clear for Each Counter

•Typical Max Count Frequency of 50 MHz

•Input Clamp Diodes Minimize High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

SN54 / 74LS390

VCC		CP0		MR Q0				CP1		Q1		Q2		Q3
16		15		14		13		12		11		10		9

	1			2			3		4		5			6			7			8
	CP0			MR			Q0		CP1		Q1			Q2			Q3			GND
																								NOTE:
																								The Flatpak version
							SN54 / 74LS393																	has the same pinouts
																								(Connection Diagram) as
		VCC				CP		MR		Q0		Q1				Q2			Q3					the Dual In-Line Package.
		14			13			12		11		10				9		8

1 2 3 4 5 6 7

CP MR Q0 Q1 Q2 Q3 GND

SN54/74LS390

SN54/74LS393

DUAL DECADE COUNTER;

DUAL 4-STAGE

BINARY COUNTER

LOW POWER SCHOTTKY

			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1
			J SUFFIX
			CERAMIC
			CASE 632-08
14	1
			N SUFFIX
			PLASTIC
14			CASE 646-06
	1
			D SUFFIX
	14		SOIC
			CASE 751A-02
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

FAST AND LS TTL DATA

5-544

SN54/74LS390 •SN54/74LS393

PIN NAMES			LOADING (Note a)
			HIGH		LOW
CP		Clock (Active LOW going edge)
					1.0	U.L.
		Input to +16 (LS393)	0.5	U.L.
CP0		Clock (Active LOW going edge)
		Input to 2 (LS390)	0.5	U.L.	1.0	U.L.
CP1		Clock (Active LOW going edge)
		Input to 5 (LS390)	0.5	U.L.	1.5	U.L.
MR		Master Reset (Active HIGH) Input	0.5	U.L.	0.25	U.L.
Q0 ± Q3		Flip-Flop outputs (Note b)	10	U.L.	5 (2.5)	U.L.

NOTES:

a)1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

b)The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b)Temperature Ranges.

FUNCTIONAL DESCRIPTION

Each half of the SN54/74LS393 operates in the Modulo 16 binary sequence, as indicated in the 16 Truth Table. The first flip-flop is triggered by HIGH-to-LOW transitions of the CP input signal. Each of the other flip-flops is triggered by a HIGH-to-LOW transition of the Q output of the preceding flip-flop. Thus state changes of the Q outputs do not occur simultaneously. This means that logic signals derived from combinations of these outputs will be subject to decoding spikes and, therefore, should not be used as clocks for other counters, registers or flip-flops. A HIGH signal on MR forces all outputs to the LOW state and prevents counting.

Each half of the LS390 contains a 5 section that is independent except for the common MR function. The 5

section operates in 4.2.1 binary sequence, as shown in the 5 Truth Table, with the third stage output exhibiting a 20% duty cycle when the input frequency is constant. To obtain a 10 function having a 50% duty cycle output, connect the input signal to CP1 and connect the Q3 output to the CP0 input; the Q0 output provides the desired 50% duty cycle output. If the input frequency is connected to CP0 and the Q0 output is connected to CP1, a decade divider operating in the 8.4.2.1 BCD code is obtained, as shown in the BCD Truth Table. Since the flip-flops change state asynchronously, logic signals derived from combinations of LS390 outputs are also subject to decoding spikes. A HIGH signal on MR forces all outputs LOW and prevents counting.

SN54 / 74LS390 LOGIC DIAGRAM (one half shown)

CP1

CP0

K CP J

K CP J

K CP J

K CP J

CD

Q

CD

Q

CD

Q

CD

Q

MR

Q0

Q1

Q2

Q3

SN54 / 74LS393 LOGIC DIAGRAM (one half shown)

CP

	K CP J	K CP	J	K CP J		K CP J
CD		CD	CD		CD
	Q		Q	Q		Q
MR
	Q0		Q1	Q2		Q3

FAST AND LS TTL DATA

5-545

SN54/74LS390 •SN54/74LS393

SN54 / 74LS390 BCD

TRUTH TABLE (Input on CP0; Q0 CP1)

COUNT		OUTPUTS
	Q3	Q2	Q1	Q0
0	L	L	L	L
1	L	L	L	H
2	L	L	H	L
3	L	L	H	H
4	L	H	L	L
5	L	H	L	H
6	L	H	H	L
7	L	H	H	H
8	H	L	L	L
9	H	L	L	H

SN54/ 74LS390 5

TRUTH TABLE (Input on CP1)

OUTPUTS

		COUNT
			Q3	Q2	Q1
	0		L	L	L
	1		L	L	H
	2		L	H	L
	3		L	H	H
	4		H	L	L

SN54 / 74LS390 10 (50% @ Q0)

TRUTH TABLE (Input on CP1, Q3 to CP0)

	COUNT		OUTPUTS
		Q3	Q2	Q1	Q0
	0	L	L	L	L
	1	L	L	H	L
	2	L	H	L	L
	3	L	H	H	L
	4	H	L	L	L
	5	L	L	L	H
	6	L	L	H	H
	7	L	H	L	H
	8	L	H	H	H
	9	H	L	L	H

GUARANTEED OPERATING RANGES

SN54 / 74LS393

TRUTH TABLE

COUNT		OUTPUTS
	Q3	Q2	Q1	Q0
0	L	L	L	L
1	L	L	L	H
2	L	L	H	L
3	L	L	H	H
4	L	H	L	L
5	L	H	L	H
6	L	H	H	L
7	L	H	H	H
8	H	L	L	L
9	H	L	L	H
10	H	L	H	L
11	H	L	H	H
12	H	H	L	L
13	H	H	L	H
14	H	H	H	L
15	H	H	H	H

H = HIGH Voltage Level

L = LOW Voltage Level

Symbol	Parameter		Min	Typ	Max	Unit
VCC	Supply Voltage	54	4.5	5.0	5.5	V
		74	4.75	5.0	5.25
TA	Operating Ambient Temperature Range	54	± 55	25	125	°C
		74	0	25	70
IOH	Output Current Ð High	54, 74			± 0.4	mA
IOL	Output Current Ð Low	54			4.0	mA
		74			8.0

FAST AND LS TTL DATA

5-546