Motorola SN54LS379J, SN54LS377J, SN54LS378J, SN74LS377D, SN74LS377DW Datasheet

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

The SN54 /74LS377 is an 8-bit register built using advanced Low Power Schottky technology. This register consists of eight D-type flip-flops with a buffered common clock and a buffered common clock enable.

The SN54/74LS378 is a 6-Bit Register with a buffered common enable. This device is similar to the SN54/74LS174, but with common Enable rather than common Master Reset.

The SN54/74LS379 is a 4-Bit Register with buffered common Enable. This device is similar to the SN54/74LS175 but features the common Enable rather then common Master Reset.

•8-Bit High Speed Parallel Registers

•Positive Edge-Triggered D-Type Flip Flops

•Fully Buffered Common Clock and Enable Inputs

•True and Complement Outputs

•Input Clamp Diodes Limit High Speed Termination Effects

PIN NAMES			LOADING (Note a)
			HIGH		LOW
E		Enable (Active LOW) Input	0.5	U.L.	0.25	U.L.
D0 ± D3		Data Inputs	0.5	U.L.	0.25	U.L.
CP		Clock (Active HIGH Going Edge) Input	0.5	U.L.	0.25	U.L.
Q0 ± Q3		True Outputs (Note b)	10	U.L.	5 (2.5)	U.L.
Q0 ± Q3		Complemented Outputs (Note b)	10	U.L.	5 (2.5)	U.L.

NOTES:

a)1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

b)The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

SN54/74LS377

SN54/74LS378

SN54/74LS379

OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE

LOW POWER SCHOTTKY

			J SUFFIX
			CERAMIC
20			CASE 732-03
1
			N SUFFIX
			PLASTIC
20			CASE 738-03
1
			DW SUFFIX
20			SOIC
			CASE 751D-03
		1
			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXDW SOIC

SN74LSXXXD SOIC

FAST AND LS TTL DATA

5-533

SN54/74LS377 •SN54/74LS378 •SN54/74LS379

CONNECTION DIAGRAM DIPS (TOP VIEW)

SN54 / 74LS377

	VCC Q7				D7		D6		Q6		Q5		D5		D4		Q4		CP
	20		19		18		17		16		15		14		13		12		11

NOTE:

The Flatpak version has the same pinouts

(Connection Diagram) as the Dual In-Line Package.

	1		2		3		4		5		6		7		8		9		10
	E		Q0		D0		D1		Q1		Q2		D2		D3		Q3		GND

SN54 / 74LS378

	VCC		Q5		D5		D4		Q4		D3		Q3		CP
	16		15		14		13		12		11		10		9

NOTE:

The Flatpak version has the same pinouts

(Connection Diagram) as the Dual In-Line Package.

	1		2		3		4		5		6		7		8
	E		Q0		D0		D1		Q1		D2		Q2		GND

SN54 / 74LS379

	VCC		Q3		Q3		D3		D2		Q2		Q2		CP
	16		15		14		13		12		11		10		9

NOTE:

The Flatpak version has the same pinouts

(Connection Diagram) as the Dual In-Line Package.

	1		2		3		4		5		6		7		8
	E		Q0		Q0		D0		D1		Q1		Q1		GND

FAST AND LS TTL DATA

5-534

SN54/74LS377 •SN54/74LS378 •SN54/74LS379

LOGIC DIAGRAMS

SN54 / 74LS377

3	4	7	8	13	14	17	18
D0	D1	D2	D3	D4	D5	D6	D7
E
ENABLE
1

CP

CLOCK

11	CP D	CP D	CP D	CP D	CP D	CP D	CP D	CP D
	Q	Q	Q	Q	Q	Q	Q	Q
	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
	2	5	6	9	12	15	16	19

SN54 / 74LS378

SN54 / 74LS379

3	4	6	11	13	14
D0	D1	D2	D3	D4	D5

CP

9
CP	D	CP	D	CP	D	CP	D	CP	D	CP	D
E		E		E		E		E		E
	Q		Q		Q		Q		Q		Q
1
E
	Q0		Q1		Q2		Q3		Q4		Q5

2	5	7	10	12	15
	4	5	12		13
	D0	D1	D2		D3

CP

9
CP	D	CP	D	CP	D	CP	D
E		E		E		E
Q	Q	Q	Q	Q	Q	Q	Q
1
E
Q0	Q0	Q1	Q1	Q2	Q2	Q3	Q3
3	2	6	7	11	10	14	15

FAST AND LS TTL DATA

5-535