Motorola SN54LS322AJ, SN74LS322AN, SN74LS322ADW Datasheet

8-BIT SHIFT REGISTERS WITH SIGN EXTEND

These 8-bit shift registers have multiplexed input/output data ports to accomplish full 8-bit data handling in a single 20-pin package. Serial data may enter the shift-right register through either D0 or D1 inputs as selected by the data select pin. A serial output is also provided. Synchronous parallel loading is achieved by taking the register enable and the S/P inputs low. This places the three-state input/output ports in the data input mode. Data is entered on the low-to-high clock transition. The data extend function repeats the sign in the QA flip-flop during shifting. An overriding clear input clears the internal registers when taken low whether the outputs are enabled or off. The output enable does not affect synchronous operation of the register.

•Multiplexed Inputs/Outputs Provide Improved Bit Density

•Sign Extend Function

•Direct Overriding Clear

•3-State Outputs Drive Bus Lines Directly

(TOP VIEW)

DATA

SIGN

VCC SELECT EXTEND

D1

B/QB

D/QD

F/QF

H/QH

Q/H

CLOCK

20

19

18

17

16

15

14

13

12

11

DS

SE

D1

B/Q

B

D/Q

D

F/QF

H/GH

Q/

H

CK

G

S/P

D0

A/QA

C/Q

C

E/QE

G/QG

OE

CLR

1

2

3

4

5

6

7

8

9

10

REGISTER S/P

D0

A/QA

C/QC

E/QE

G/QG OUTPUT CLEAR

GND

ENABLE

ENABLE

GUARANTEED OPERATING RANGES

SN54/74LS322A

8-BIT SHIFT REGISTERS WITH SIGN EXTEND

LOW POWER SCHOTTKY

		J SUFFIX
		CERAMIC
	20	CASE 732-03
	1
		N SUFFIX
		PLASTIC
	20	CASE 738-03
	1
		DW SUFFIX
	20	SOIC
		CASE 751D-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXDW SOIC

Symbol		Parameter		Min	Typ	Max	Unit
VCC	Supply Voltage		54	4.5	5.0	5.5	V
			74	4.75	5.0	5.25
TA	Operating Ambient Temperature Range		54	± 55	25	125	°C
			74	0	25	70
IOH	Output Current Ð High	Q H′	54, 74			± 0.4	mA
IOL	Output Current Ð Low	Q H′	54			4.0	mA
		QH′	74			8.0
IOH	Output Current Ð High	Q A± QH	54			± 1.0	mA
		QA± QH	74			± 2.6
IOL	Output Current Ð Low	Q A± QH	54			12	mA
		QA± QH	74			24

FAST AND LS TTL DATA

5-1

		SN54/74LS322A
			BLOCK DIAGRAM
REGISTER		(1)
ENABLE
G
S/P		(2)
SIGN		(18)
EXTEND
SE		(17)
	D1
DATA		(19)
SELECT
DS		(3)
D0
					FOUR
					IDENTICAL
					CHANNELS
			Q	Q	NOT		Q		Q	(12)
					SHOWN					QH
		CK		CK		CK		CK
		D	Q	D Q		D	Q	D	Q
		CLR		CLR		CLR		CLR
CLOCK		(11)
CLEAR		(9)
OUTPUT		(8)
ENABLE
OE
			(4)	(16)			(7)		(13)
			A/QA	B/QB			G/QG		H/QH

FUNCTION TABLE

INPUTS

INPUTS/OUTPUTS

OUTPUT

OPERATION

REGISTER

SIGN

DATA

OUTPUT

C/QC …

QH′

CLEAR

S/P

CLOCK

A/QA

B/QB

H/QH

ENABLE

EXTEND

SELECT

ENABLE

Clear

L

H

X

X

X

L

X

L

L

L

L

L

L

X

H

X

X

L

X

L

L

L

L

L

Hold

H

H

X

X

X

L

X

QA0

QB0

QC0

QH0

QH0

Shift Right

H

L

H

H

L

L

↑

D0

QAn

QBn

QGn

QGn

H

L

H

H

H

L

↑

D1

QAn

QBn

QGn

QGn

Sign Extend

H

L

H

L

X

L

↑

QAn

QAn

QBn

QGn

QGn

Load

H

L

L

X

X

X

↑

a

b

c

h

h

When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. If both the register enable input and the S/P input are low while the clear input is low, the register is cleared while the eight input/output terminals are disabled to the high-impedance state.

H = HIGH Level (steady state) L = LOW Level (steady state)

X = Irrelevant (any input, including transitions) ↑ = Transition from LOW to HIGH level

QA0… QH0 = the level of QA through QH, respectively, before the indicated steady-state conditions were established QAn… QHn = the level of QA through QH, respectively, before the most recent ↑ transition of the clock

D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively a… h = the level of steady-state inputs at inputs A through H respectively

FAST AND LS TTL DATA

5-2