Motorola SN54LS166J, SN74LS166D, SN74LS166N Datasheet

8-BIT SHIFT REGISTERS

The SN54L/74LS166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 54/74LS standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified.

The LS166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.

•Synchronous Load

•Direct Overriding Clear

•Parallel to Serial Conversion

	PARALLEL			PARALLEL INPUTS
SHIFT/ INPUT OUTPUT
VCC	LOAD	H	QH	G	F	E	CLEAR
16	15	14	13	12	11	10	9
	SHIFT/	H	QH	G	F	E
	LOAD
	SERIAL INPUT				CLEAR
					CLOCK
	A	B	C	D		CK
					INHIBIT
1	2	3	4	5	6	7	8
SERIAL	A	B	C	D	CLOCK CLOCK GND
INPUT					INHIBIT

PARALLEL INPUTS

SN54/74LS166

8-BIT SHIFT REGISTERS

LOW POWER SCHOTTKY

			J SUFFIX
			CERAMIC
			CASE 620-09
16	1
			N SUFFIX
			PLASTIC
16			CASE 648-08
	1
			D SUFFIX
	16		SOIC
			CASE 751B-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

FUNCTION TABLE

			INPUTS				INTERNAL		OUTPUT
	SHIFT/	CLOCK				PARALLEL	OUTPUTS
CLEAR				CLOCK	SERIAL				QH
	LOAD	INHIBIT				A . . . H	QA	QB
L	X	X		X	X	X	L	L	L
H	X	L		L	X	X	QA0	QB0	QH0
H	L	L		↑	X	a . . . h	a	b	h
H	H	L		↑	H	X	H	QAn	QGn
H	H	L		↑	L	X	L	QAn	QGn
H	X	H		↑	X	X	QA0	QB0	QH0

FAST AND LS TTL DATA

5-1

SN54/74LS166

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

CLOCK
CLOCK INIHIBIT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A	H
B	L
C	H
PARALLEL D	L
INPUTS	H
E
F	L
G	H
H	H
OUTPUT QH	INHIBIT H H	L	H	L	H	L	H
SERIAL SHIFT			SERIAL SHIFT

CLEAR

CLEAR

SERIAL INPUT

SHIFT/LOAD

A

B

C

D

E

F

G

H

CLOCK

CLOCK INHIBIT

	LOAD
(9)
(1)
(15)
(2)
	R	S
		CK
(3)		QA
	R	S
		CK
(4)		QB
	R	S
		CK
(5)		QC
	R	S
		CK
(10)		QD
	R	S
		CK
(11)		QE
	R	S
		CK
(12)		QF
	R	S
		CK
(14)		QG
(7)	R	S
		CK

(6)	(13) QH

FAST AND LS TTL DATA

5-2