Motorola SN54LS273J, SN74LS273N, SN74LS273DW Datasheet

OCTAL D FLIP-FLOP WITH CLEAR

The SN54/74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.

•8-Bit High Speed Register

•Parallel Register

•Common Clock and Master Reset

•Input Clamp Diodes Limit High-Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

SN54/74LS273

OCTAL D FLIP-FLOP

WITH CLEAR

LOW POWER SCHOTTKY

	VCC Q7				D7		D6		Q6		Q5		D5		D4		Q4		CP
	20		19		18		17		16		15		14		13		12		11

1

2

3

4

5

6

7

8

9

10

MR

Q0

D0

D1

Q1

Q2

D2

D3

Q3

GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

CP

Clock (Active HIGH Going Edge) Input

0.5

U.L.

0.25

U.L.

D0 ± D7

Data Inputs

0.5

U.L.

0.25

U.L.

MR

Master Reset (Active LOW) Input

0.5

U.L.

0.25

U.L.

Q0 ± Q7

Register Outputs (Note b)

10

U.L.

5 (2.5)

U.L.

NOTES:

a)1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.

b)The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.

TRUTH TABLE

	MR		CP			Dx	Qx
	L		X			X	L
	H					H	H
	H					L	L

		J SUFFIX
		CERAMIC
	20	CASE 732-03
	1
		N SUFFIX
		PLASTIC
	20	CASE 738-03
	1
		DW SUFFIX
	20	SOIC
		CASE 751D-03
		1

ORDERING INFORMATION

SN54LSXXXJ Ceramic

SN74LSXXXN Plastic

SN74LSXXXDW SOIC

H = HIGH Logic Level

L = LOW Logic Level

X = Immaterial

LOGIC DIAGRAM			3	4	7	8	13	14	17	18
	11		D0	D1	D2	D3	D4	D5	D6	D7
	CP
		CP D		CP D	CP D	CP D	CP D	CP D	CP D	CP D
	1	CD	Q	CD Q	CD Q	CD Q	CD Q	CD Q	CD Q	CD Q
MR
VCC = PIN 20
GND	= PIN	10
=	PIN	NUMBERS	Q0	Q1	Q2	Q3	Q4	Q5	Q6	Q7
			2	5	6	9	12	15	16	19

FAST AND LS TTL DATA

5-447

SN54/74LS273

FUNCTIONAL DESCRIPTION

The SN54/74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset.

When the MR input is LOW, the Q outputs are LOW,

GUARANTEED OPERATING RANGES

independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input.

Symbol	Parameter		Min	Typ	Max	Unit
VCC	Supply Voltage	54	4.5	5.0	5.5	V
		74	4.75	5.0	5.25
TA	Operating Ambient Temperature Range	54	± 55	25	125	°C
		74	0	25	70
IOH	Output Current Ð High	54, 74			± 0.4	mA
IOL	Output Current Ð Low	54			4.0	mA
		74			8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

				Limits
Symbol	Parameter		Min	Typ	Max	Unit		Test Conditions
VIH	Input HIGH Voltage		2.0			V	Guaranteed Input HIGH Voltage for
							All Inputs
VIL	Input LOW Voltage	54			0.7	V	Guaranteed Input LOW Voltage for
		74			0.8		All Inputs
VIK	Input Clamp Diode Voltage			± 0.65	± 1.5	V	VCC = MIN, IIN = ±18 mA
VOH	Output HIGH Voltage	54	2.5	3.5		V	VCC = MIN, IOH = MAX, VIN = VIH
		74	2.7	3.5		V	or VIL per Truth Table
		54, 74		0.25	0.4	V	I = 4.0 mA		VCC = VCC MIN,
VOL	Output LOW Voltage						OL		VIN = VIL or VIH
		74		0.35	0.5	V	IOL = 8.0 mA
									per Truth Table
IIH	Input HIGH Current				20	μA	VCC = MAX, VIN = 2.7 V
					0.1	mA	VCC = MAX, VIN = 7.0 V
IIL	Input LOW Current				± 0.4	mA	VCC = MAX, VIN = 0.4 V
IOS	Short Circuit Current (Note 1)		± 20		± 100	mA	VCC = MAX
ICC	Power Supply Current				27	mA	VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

			Limits
Symbol	Parameter				Unit	Test Conditions
		Min	Typ	Max
fMAX	Maximum Input Clock Frequency	30	40		MHz	Figure 1
tPHL	Propagation Delay, MR to Q Output		18	27	ns	Figure 2
tPLH	Propagation Delay, Clock to Output		17	27	ns	Figure 1
tPHL			18	27

FAST AND LS TTL DATA

5-448