MOTOROLA SN74LS193D, SN74LS193DR2, SN74LS193M, SN74LS193MEL, SN74LS193ML1 Datasheet
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PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks.
•Low Power . . . 95 mW Typical Dissipation
•High Speed . . . 40 MHz Typical Count Frequency
•Synchronous Counting
•Asynchronous Master Reset and Parallel Load
•Individual Preset Inputs
•Cascading Circuitry Internally Provided
•Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
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VCC |
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P0 |
MR |
TCD |
TCU |
PL |
P2 |
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P3 |
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NOTE: |
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The Flatpak version |
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has the same pinouts |
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(Connection Diagram) as |
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the Dual In-Line Package. |
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P1 |
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Q1 |
Q0 |
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CPD |
CPU |
Q2 |
Q3 |
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GND |
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PIN NAMES |
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LOADING (Note a) |
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HIGH |
LOW |
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CPU |
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Count Up Clock Pulse Input |
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0.5 |
U.L. |
0.25 |
U.L. |
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CPD |
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Count Down Clock Pulse Input |
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0.5 |
U.L. |
0.25 |
U.L. |
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MR |
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Asynchronous Master Reset (Clear) Input |
0.5 |
U.L. |
0.25 |
U.L. |
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PL |
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Asynchronous Parallel Load (Active LOW) Input |
0.5 |
U.L. |
0.25 |
U.L. |
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Pn |
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Parallel Data Inputs |
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0.5 |
U.L. |
0.25 |
U.L. |
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Qn |
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Flip-Flop Outputs (Note b) |
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10 |
U.L. |
5 (2.5) |
U.L. |
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TCD |
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Terminal Count Down (Borrow) Output (Note b) |
10 |
U.L. |
5 (2.5) |
U.L. |
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TCU |
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Terminal Count Up (Carry) Output (Note b) |
10 |
U.L. |
5 (2.5) |
U.L. |
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NOTES:
a.1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b.The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
SN54/74LS192
SN54/74LS193
PRESETTABLE BCD/DECADE
UP/DOWN COUNTER
PRESETTABLE 4-BIT BINARY
UP/DOWN COUNTER
LOW POWER SCHOTTKY
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J SUFFIX |
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CERAMIC |
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CASE 620-09 |
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1 |
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N SUFFIX |
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PLASTIC |
16 |
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CASE 648-08 |
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1 |
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D SUFFIX |
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16 |
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SOIC |
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CASE 751B-03 |
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1 |
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ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
11 15 1 10 9
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PL |
P0 |
P1 |
P2 |
P3 |
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12 |
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5 |
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CPU |
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TCU |
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4 |
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CPD |
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TC |
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13 |
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MR Q0 |
Q1 |
Q2 |
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D |
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Q3 |
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7 |
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14 |
3 |
2 |
6 |
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VCC = PIN 16 |
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GND = PIN 8 |
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FAST AND LS TTL DATA
5-1
SN54/74LS192 •SN54/74LS193
STATE DIAGRAMS |
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0 |
1 |
2 |
3 |
4 |
15 |
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5 |
14 |
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6 |
13 |
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7 |
12 |
11 |
10 |
9 |
8 |
LS192
LS192 LOGIC EQUATIONS FOR TERMINAL COUNT
TCU = Q0 Q3 CPU
TCD = Q0 Q1 Q2 Q3 CPD
LS193 LOGIC EQUATIONS FOR TERMINAL COUNT
TCU = Q0 Q1 Q2 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD
COUNT UP
COUNT DOWN
0 |
1 |
2 |
3 |
4 |
15 |
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5 |
14 |
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6 |
13 |
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7 |
12 |
11 |
10 |
9 |
8 |
LS193
LOGIC DIAGRAMS |
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P0 |
P1 |
P2 |
P3 |
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PL |
11 |
15 |
1 |
10 |
9 |
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(LOAD) |
5 |
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CPU |
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12 |
TCU |
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(UP COUNT) |
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(CARRY |
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OUTPUT) |
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SD Q |
SD Q |
SD Q |
SD Q |
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T |
T |
T |
T |
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CDQ |
CDQ |
CDQ |
CDQ |
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13 |
TCD |
CPD |
4 |
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(BORROW |
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OUTPUT) |
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(DOWN |
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COUNT) |
14 |
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MR |
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(CLEAR) |
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3 |
2 |
6 |
7 |
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Q0 |
Q1 |
Q2 |
Q3 |
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VCC = PIN 16 |
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LS192 |
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GND = PIN 8 |
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= PIN NUMBERS |
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FAST AND LS TTL DATA
5-2
SN54/74LS192 •SN54/74LS193
LOGIC DIAGRAMS (continued) |
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P0 |
P1 |
P2 |
P3 |
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PL |
11 |
15 |
1 |
10 |
9 |
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(LOAD) |
5 |
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CPU |
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TC |
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12 |
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(UP COUNT) |
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U |
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(CARRY |
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OUTPUT) |
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SD Q |
SDQ |
SD Q |
SD Q |
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T |
T |
T |
T |
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CDQ |
CDQ |
CDQ |
CDQ |
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13 |
TCD |
CPD |
4 |
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(BORROW |
(DOWN |
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OUTPUT) |
COUNT) |
14 |
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MR |
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(CLEAR) |
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3 |
2 |
6 |
7 |
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Q0 |
Q1 |
Q2 |
Q3 |
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LS193 |
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VCC = PIN 16 |
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GND = PIN 8 |
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= PIN NUMBERS |
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FAST AND LS TTL DATA
5-3
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