DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
Q |
5(9) |
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6(8)Q |
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CLEAR |
(C) |
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4(10) |
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D |
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TO |
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SET |
(S) |
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D |
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OTHER |
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K |
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FLIP"FLOP |
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J |
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2(12) |
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3(11) |
13 |
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CLOCK |
(CP) |
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MODE SELECT Ð TRUTH TABLE
OPERATING MODE |
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INPUTS |
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OUTPUTS |
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SD |
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CD |
J |
K |
Q |
Q |
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Set |
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L |
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H |
X |
X |
H |
L |
Reset (Clear) |
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H |
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L |
X |
X |
L |
H |
*Undetermined |
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L |
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L |
X |
X |
H |
H |
Toggle |
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H |
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H |
h |
h |
q |
q |
Load ª0º (Reset) |
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H |
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H |
l |
h |
L |
H |
Load ª1º (Set) |
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H |
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H |
h |
l |
H |
L |
Hold |
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H |
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H |
l |
l |
q |
q |
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*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level X = Don't Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
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J SUFFIX |
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CERAMIC |
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CASE 632-08 |
14 |
1 |
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N SUFFIX |
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PLASTIC |
14 |
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CASE 646-06 |
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1 |
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D SUFFIX |
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14 |
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SOIC |
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CASE 751A-02 |
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1 |
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ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
410
3 |
J SD Q |
5 |
11 J SD Q |
9 |
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13 |
CP |
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CP |
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2 |
K C |
Q |
6 |
12 K C |
Q |
8 |
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D |
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D |
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1 |
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VCC = PIN 14 |
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GND |
= PIN 7 |
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FAST AND LS TTL DATA
5-193
SN54/74LS114A
GUARANTEED OPERATING RANGES
Symbol |
Parameter |
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Min |
Typ |
Max |
Unit |
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VCC |
Supply Voltage |
54 |
4.5 |
5.0 |
5.5 |
V |
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74 |
4.75 |
5.0 |
5.25 |
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TA |
Operating Ambient Temperature Range |
54 |
± 55 |
25 |
125 |
°C |
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74 |
0 |
25 |
70 |
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IOH |
Output Current Ð High |
54, 74 |
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± 0.4 |
mA |
IOL |
Output Current Ð Low |
54 |
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4.0 |
mA |
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74 |
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8.0 |
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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
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Limits |
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Symbol |
Parameter |
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Unit |
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Test Conditions |
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Min |
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Max |
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VIH |
Input HIGH Voltage |
2.0 |
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V |
Guaranteed Input HIGH Voltage for |
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All Inputs |
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VIL |
Input LOW Voltage |
54 |
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0.7 |
V |
Guaranteed Input LOW Voltage for |
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74 |
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0.8 |
All Inputs |
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VIK |
Input Clamp Diode Voltage |
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± 0.65 |
± 1.5 |
V |
VCC = MIN, IIN = ±18 mA |
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VOH |
Output HIGH Voltage |
54 |
2.5 |
3.5 |
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V |
VCC = MIN, IOH = MAX, VIN = VIH |
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74 |
2.7 |
3.5 |
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V |
or VIL per Truth Table |
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54, 74 |
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0.25 |
0.4 |
V |
I = 4.0 mA |
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VCC = VCC MIN, |
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VOL |
Output LOW Voltage |
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OL |
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VIN = VIL or VIH |
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74 |
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0.35 |
0.5 |
V |
IOL = 8.0 mA |
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per Truth Table |
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J, K |
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20 |
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Set |
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60 |
μA |
VCC = MAX, VIN = 2.7 V |
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Clear |
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120 |
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IIH |
Input HIGH Current |
Clock |
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160 |
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J, K |
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0.1 |
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Set |
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0.3 |
mA |
VCC = MAX, VIN = 7.0 V |
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Clear |
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0.6 |
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Clock |
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0.8 |
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J, K |
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± 0.4 |
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IIL |
Input LOW Current |
Set |
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± 0.8 |
mA |
VCC = MAX, VIN = 0.4 V |
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Clear, Clock |
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± 1.6 |
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IOS |
Output Short Circuit Current (Note 1) |
± 20 |
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± 100 |
mA |
VCC = MAX |
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ICC |
Power Supply Current |
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6.0 |
mA |
VCC = MAX |
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Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. |
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AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) |
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Limits |
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Symbol |
Parameter |
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Unit |
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Test Conditions |
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Min |
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Typ |
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Max |
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fMAX |
Maximum Clock Frequency |
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30 |
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45 |
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MHz |
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VCC = 5.0 V |
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tPLH |
Propagation Delay, Clock, |
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15 |
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20 |
ns |
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CL = 15 pF |
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tPHL |
Clear, Set to Output |
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15 |
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20 |
ns |
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AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) |
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Limits |
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Symbol |
Parameter |
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Unit |
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Test Conditions |
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Min |
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Typ |
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Max |
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tW |
Clock Pulse Width High |
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20 |
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ns |
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tW |
Clear, Set Pulse Width |
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25 |
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ns |
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VCC = 5.0 V |
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ts |
Setup Time |
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20 |
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ns |
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th |
Hold Time |
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0 |
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ns |
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FAST AND LS TTL DATA
5-194
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