Motorola MPC2106SG66, MPC2107, MPC2107SG66, MPC2105SG66, MPC2106 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MPC2104/D

Advance Information

256KB and 512KB BurstRAM

Secondary Cache Modules for PowerPC PReP/CHRP Platforms

The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs.

The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola's 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used.

Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal.

Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control.

The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the address latch.

Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in±depth description of the cache module. This EEPROM will be available on future revisions of the module family.

The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected.

All of these cache modules are plug and pin compatible with each other.

•PowerPC±style Burst Counter on Chip (MPC2104/5/6)

•Flow±Through Data I/O (MPC2104/5/6)

•Plug and Pin Compatibility of entire Module Family

•Multiple Clock Pins for Reduced Loading

•All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6)

•Three State Outputs

•Byte Write Capability

•Fast Module Clock Rates: Up to 66 MHz

•Fast SRAM Access Times: 10 ns for Tag RAM Match

9 ns for Data RAM (MPC2104/5/6)

15 ns for Data RAM (MPC2107)

•Decoupling Capacitors for Each Fast Static RAM

•High Quality Multi±Layer FR4 PWB With Separate Power and Ground Planes

•182 Pin Card Edge Module

•Burndy Connector, Part Number: ELF182JSC±3Z50

BurstRAM is a trademark of Motorola.

PowerPC is a trademark of International Business Machines Corp.

MPC2104

MPC2105

MPC2106

MPC2107

This document contains information on a new product. Specifications and information herein are subject to change without notice.

11/8/95

MOTOROLA FAST SRAM	MPC2104
Motorola, Inc. 1995	•

1

PIN ASSIGNMENT

182±LEAD DIMM

TOP VIEW ± CASE TBD

NOTES:

1. VCC5 and VCC3 must be connected on all modules.

	VSS			92	1		VSS
PD1/IDSDATA				93	2		PD0/IDSCLK
	PD3			94	3		PD2
	DH31			95	4		DH30
	DH29			96	5		DH28
	DH27			97	6		DH26
	DH25			98	7		DH24
	VCC3			99	8		VCC3
	CWE3			100	9		DP3
	DH23			101	10		DH22
	DH21			102	11		DH20
	DH18			103	12		DH19
	VSS			104	13		VSS
	DH16			105	14		DH17
	CWE2			106	15		DP2
	DH14			107	16		DH15
	DH13			108	17		DH12
	VCC5			109	18		VCC5
	DH10			110	19		DH11
	DH8			111	20		DH9
	CWE1			112	21		DP1
	DH6			113	22		DH7
	VCC3			114	23		VCC3
	DH4			115	24		DH5
	VSS			116	25		DH3
	CLK0			117	26		DH2
	VSS			118	27		DH0
	DH1			119	28		DP0
	CWE0			120	29		VSS
	DL31			121	30		CLK1
	DL30			122	31		VSS
	VSS			123	32		DL28
	DL29			124	33		DL26
	DL27			125	34		DL24
	DL25			126	35		DP7
	VCC5			127	36		VCC5
	CWE7			128	37		DL22
	DL23			129	38		DL20
	DL21			130	39		DL18
	DL19			131	40		DL16
	VSS			132	41		VSS
	DL17			133	42		DP6
					43	DL14
	CWE6			134
	DL15			135	44	DL12
	DL13			136	45	DL11
	VSS			137	46	VSS
	DL10			138	47	DL9
	DL8			139	48	DP5
				140	49	DL7
CWE5
	DL6			141	50	DL4
	VCC3			142	51	VCC3
	DL5			143	52	DL3
	DL2			144	53	DL1
	VSS			145	54	DL0
	CLK3			146	55	VSS
	VSS			147	56	CLK2
	CLK4			148	57	VSS
	VSS			149	58		DP4
CWE4				150	59	COE0
	ALE			151	60	COE1
	VCC3			152	61	VCC3
ADDR1				153	62	ADDR0
RESERVED				154	63	RESERVED
CNTEN0				155	64	ADS0
CNTEN1				156	65	ADS1
	VCC5			157	66	VCC5
	VCC5			158	67	VCC5
	A27			159	68	A28
	A24			160	69	A26
	A22			161	70	A25
	A20			162	71	A23
	VSS			163	72	VSS
	A18			164	73	A21
	A16			165	74	A19
	A15			166	75	A17
	A14			167	76	A13
	VCC3			168	77	VCC3
	A10			169	78	A12
	A8			170	79	A11
	A6			171	80	A9
	VSS			172	81	VSS
	A4			173	82	A7
	A2			174	83	A5
	A1			175	84	A3
BURSTMODE				176	85	A0
	VCC5			177	86	VCC5
VALIDIN				178	87	TCLR
	TWE			179	88	MATCH
STANDBY				180	89	TOE
DIRTYOUT				181	90	DIRTYIN
	VSS			182	91	VSS

MPC2104•MPC2105•MPC2106•MPC2107	MOTOROLA FAST SRAM
2

MPC2104/MPC2105 BLOCK DIAGRAM

A28

A27

A14 ± A26

A13

ADS0

CNTEN0

COE0

STANDBY VCC5 via 100 Ω

A14 ± A26

A2 ± A12

A1

TCLR

TWE

CLK2

VALIDIN

DIRTYIN

TOE

		A0 MCM67Mx18		CLK0	CLK3	= NC
		A1	K		CLK4	= NC
	'244	A2 ± A14	DQ0 ± DQ8	DH0 ± DH7 + DP0	ALE	= NC
		A15	DQ9 ± DQ17	DH8 ± DH15 + DP1	ADS1	= NC
					CNTEN1	= NC
		TSC	LW	CWE0
					COE1	= NC
		BAA	UW	CWE1
					ADDR0	= NC
		G			ADDR1	= NC
		E			PD2	= NC
					PD3
		TSP				J4

A0	MCM67Mx18
A1		K	CLK0
A2 ± A14		DQ0 ± DQ8	DH16 ± DH23 + DP2
A15		DQ9 ± DQ17	DH24 ± DH31 + DP3
TSC		LW	CWE2
BAA		UW	CWE3		X24C00
G			PD0/IDSCLK	PD1/IDSDATA	(OPTIONAL)
E
					SCL
			J2
TSP				J3	SDA

A0

MCM67Mx18

CLK1

A1

K

A2 ± A14

DQ0 ± DQ8

DL0 ± DL7 + DP4

A15

DQ9 ± DQ17

DL8 ± DL15 + DP5

CWE4

LW

TSC

CWE5

UW

BAA

G

E

TSP

		A0	MCM67Mx18
		A1		K	CLK1
		A2 ± A14		DQ0 ± DQ8	DL16 ± DL23 + DP6
		A15		DQ9 ± DQ17	DL24 ± DL31 + DP7
		TSC		LW	CWE6
		BAA		UW	CWE7
		G				256KB	512KB	EEPROM	EEPROM
		E
								256KB	512KB
		TSP			J5	no stuff	0 Ω	no stuff	0 Ω
					J4	0 Ω	0 Ω	no stuff	no stuff
					J3	0 Ω	0 Ω	no stuff	no stuff
					J2	0 Ω	no stuff	no stuff	no stuff
			TAG: 16K x 12 + V + D		J1	0 Ω	no stuff	0 Ω	no stuff
	J1				J0	no stuff	0 Ω	no stuff	0 Ω
	J0	A13		TT1, WTD, E1		VSS
		A0 ± A12		SFUNC, SG
J5		TDQ0 ± TDQ10		TAG, TAD, E2		VCC5 via 100 Ω
		TDQ11		TAH, PWRDN
		RESET		MATCH		MATCH
		SW		DIRTYQ		DIRTYOUT
		TW		VCCQ		VCC3
		K
				VALIDQ		NC
		VALIDD
				WTQ		NC
		DIRTYD
		TG

Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.

MOTOROLA FAST SRAM	MPC2104•MPC2105•MPC2106•MPC2107
	3

			MPC2106 BLOCK DIAGRAM
		64K X 18 BURST
A13 ± A28	'244	A0 ± A15	K	CLK0
ADS0		TSC
			DQ0 ± DQ8	DH0 ± DH7 + DP0
CNTEN0		BAA
			DQ9 ± DQ17	DH8 ± DH15 + DP1
COE0		G								X24C00
			LW	CWE0
		PA12
A12			UW	CWE1						(OPTIONAL)
	PAL	E			PD0/IDSCLK			PD1/IDSDATA
STANDBY										SCL
							J0
		64K X 18 BURST								SDA
PA12L		A0 ± A15	K	CLK1
		TSC	DQ0 ± DQ8	DH16 ± DH23 + DP2
		BAA	DQ9 ± DQ17	DH24 ± DH31 + DP3
		G	LW	CWE2
		E	UW	CWE3				TAG: 16K x 12 + V + D
		64K X 18 BURST		A13 ± A26		14		A0 ± A13		TT1, WTD	VSS
					A0 ± A11			TDQ0 ± TDQ11		SFUNC, SG
											VCC5
		A0 ± A15	K	CLK3	TCLR			RESET	TAH, TAG, TAD
		TSC	DQ0 ± DQ8	DL0 ± DL7 + DP4	TWE			SW		PWRDN	via 100 Ω
		BAA	DQ9 ± DQ17	DL8 ± DL15 + DP5			TW			MATCH	MATCH
		G	LW	CWE4	CLK2			K		DIRTYQ	DIRTYOUT
		E	UW	CWE5	VALIDIN			VALIDD		VCCQ	VCC3
					DIRTYIN			DIRTYD
										TA, VALIDQ	NC
					TOE			TG
		64K X 18 BURST								WTQ	NC
		A0 ± A15	K	CLK4						E1	A12
		TSC	DQ0 ± DQ8	DL16 ± DL23 + DP6						E2	VDD
		BAA	DQ9 ± DQ17	DL24 ± DL31 + DP7
		G	LW	CWE6
		E	UW	CWE7				TAG: 16K x 12 + V + D

	64K X 18 BURST			A13 ± A26			A0 ± A13	TT1, WTD	VSS
				A0 ± A11			TDQ0 ± TDQ11 SFUNC, SG		VCC5
	A0 ± A15	K	CLK0		TCLR		RESET	TAH, TAG, TAD
ADS1	TSC	DQ0 ± DQ8	DH0 ± DH7 + DP0		TWE		SW	PWRDN	via 100 Ω
CNTEN1	BAA	DQ9 ± DQ17	DH8 ± DH15 + DP1		CLK2		TW	MATCH	MATCH
COE1	G	LW	CWE0				K	DIRTYQ	DIRTYOUT
	E	UW	CWE1	VALIDIN			VALIDD	VCCQ	VCC3
				DIRTYIN
							DIRTYD	TA, VALIDQ	NC
					TOE		TG
	64K X 18 BURST							WTQ	NC
	A0 ± A15	K	CLK1					E1	VSS
	TSC	DQ0 ± DQ8	DH16 ± DH23 + DP2					E2	A12
	BAA	DQ9 ± DQ17	DH24 ± DH31 + DP3
	G	LW	CWE2
	E	UW	CWE3
	64K X 18 BURST						ALE	= NC
							ADDR0	= NC
	A0 ± A15	K	CLK3				ADDR1	= NC
	TSC	DQ0 ± DQ8	DL0 ± DL7 + DP4				PD2	= NC
							PD3
	BAA	DQ9 ± DQ17	DL8 ± DL15 + DP5					J1
	G	LW	CWE4
	E	UW	CWE5
	64K X 18 BURST
	A0 ± A15	K	CLK4
	TSC	DQ0 ± DQ8	DL16 ± DL23 + DP6
	BAA	DQ9 ± DQ17	DL24 ± DL31 + DP7				1M	EEPROM 1M
	G	LW	CWE6			J1	0 Ω	no stuff
	E	UW	CWE7			J0	0 Ω	no stuff

Note: All 64K X 18 TSP signals are tied to VCC via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge connector A27 connects to the 64K x 18 A1.

MPC2104•MPC2105•MPC2106•MPC2107	MOTOROLA FAST SRAM
4

			MPC2107 BLOCK DIAGRAM
ADDR0		A0	MCM6206
ADDR1		A1
A14 ± A26	'373	A2 ± A14
ALE			DQ0 ± DQ7	DH0 ± DH7						X24C00
COE0		G	W	CWE0
										(OPTIONAL)
STANDBY		E			PD0/IDSCLK			PD1/IDSDATA
										SCL
							J2
		A0	MCM6206							SDA
								J3
		A1
		A2 ± A14		DH8 ± DH15
			DQ0 ± DQ7
		G	W	CWE1
		E
		A0	MCM6206
		A1
		A2 ± A14		DH16 ± DH23
			DQ0 ± DQ7
		G	W	CWE2
		E
		A0	MCM6206		VSS	13		A13TAG: 16K x 12 + V + D
					A14 ± A26			A0 ± A12	TT1, WTD, E1		VSS
		A1
					A2 ± A13			TDQ0 ± TDQ11		SFUNC, SG	VCC5
		A2 ± A14		DH24 ± DH31	TCLR			RESET	TAH, TAG, TAD
			DQ0 ± DQ7		TWE			SW		E2, PWRDN	via 100 Ω
			W	CWE3
		G					TW			MATCH	MATCH
					CLK2
		E						K		DIRTYQ	DIRTYOUT
			MCM6206		VALIDIN			VALIDD		VCCQ	VCC3
					DIRTYIN			DIRTYD
		A0								TA, VALIDQ	NC
					TOE			TG
		A1								WTQ	NC
		A2 ± A14		DL0 ± DL7
			DQ0 ± DQ7
COE1		G	W	CWE4
		E
		A0	MCM6206				CLK0, 1, 3, 4			= NC
		A1					ADS0, ADS1			= NC
		A2 ± A14					CNTEN0, CNTEN1 = NC
				DL8 ± DL15			A27, A28			= NC
			DQ0 ± DQ7
		G	W	CWE5			DP0 ± DP7			= NC
							BURSTMODE			= NC
		E
							PD2
			MCM6206				PD3			= NC
		A0								J1
		A1
		A2 ± A14		DL16 ± DL23
			DQ0 ± DQ7
		G	W	CWE6
		E					256KB			EEPROM 256KB
			MCM6206			J3	0 Ω			no stuff
		A0				J2	0 Ω			no stuff
		A1				J1	0 Ω			no stuff
		A2 ± A14		DL24 ± DL31
			DQ0 ± DQ7
		G	W	CWE7
		E

MOTOROLA FAST SRAM	MPC2104•MPC2105•MPC2106•MPC2107
	5

PIN DESCRIPTIONS

Pin Locations	Symbol	Type		Description
68, 69, 70, 71, 73, 74, 75, 76,	A0 ± A28	Input	Address Inputs ± (MSB:0, LSB:28)
78, 79, 80, 82, 83, 84, 85,
159, 160, 161, 162, 164, 165,
166, 167, 169, 170, 171, 173,
174, 175
62	ADDR0	Input	Least significant address bit when asynchronous Data RAMs are used.
153	ADDR1	Input	Next to least significant address bit when asynchronous Data RAMs are used.
30, 56, 117, 146, 148	CLK0 ± CLK4	Input	Clock Inputs ± CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
			For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0±CLK2
			only. For MPC2107 use CLK2 only.
4, 5, 6, 7, 10, 11, 12, 14, 16,	DH0 ± DH31	I/O	High Data Bus ± (MSB:0, LSB:31)
17, 19, 20, 22, 24, 25, 26, 27,
95, 96, 97, 98, 101, 102, 103,
105, 107, 108, 110, 111, 113,
115, 119
32, 33, 34, 37, 38, 39, 40, 43,	DL0 ± DL31	I/O	Low Data Bus ± (MSB:0, LSB:31)
44, 45, 47, 49, 50, 52, 53, 54,
121, 122, 124, 125, 126, 129,
130, 131, 133, 135, 136, 138,
139, 141, 143, 144
9, 15, 21, 28, 35, 42, 48, 58	DP0 ± DP7	I/O	Data Parity Bits ± (MSB:0, LSB:7)
3, 94	PD2, PD3	Output	Presence detect bits.
2	PD0/IDSCLK	Input	Presence detect bit 0/EEPROM serial clock. (EEPROM option only.)
93	PD1/IDSDATA	I/O	Presence detect bit 1/EEPROM serial data. (EEPROM option only.)
64, 65	ADS0, ADS1	Input	Data RAM Address Strobe ± For MPC2104 or MPC2105 use ADS0 only. For
			MPC2106 use ADS0, ADS1.
151	ALE	Input	Data RAM Address Latch Enable ± Use for asynchronous Data RAM only.
155, 156	CNTEN0,	Input	Data RAM Count Enables ± For MPC2104 or MPC2105 use CNTEN0 only. For
	CNTEN1		MPC2106 use CNTEN0, CNTEN1.
59, 60	COE0,	Input	Data RAM Output Enables ± For MPC2104 or MPC2105 use COE0 only. For
	COE1		all others use COE0, COE1.
100, 106, 112, 120,	CWE0 ± CWE7	Input	Data RAM Write Enables ± (MSB:0, LSB:7)
128, 134, 140, 150
87	TCLR	Input	Tag RAM clear.
88	MATCH	Output	Tag RAM active high match indication.
178	VALIDIN	Input	Tag RAM valid bit.
179	TWE	Input	Tag RAM write enable.
89	TOE	Input	Tag RAM output enable.
90	DIRTYIN	Input	Dirty input bit.
181	DIRTYOUT	Output	Dirty output bit.
180	STANDBY	Input	Standby pin. Reduces standby power consumption.
176, 63, 154	RESERVED		Reserved pin.
8, 23, 51, 61, 77, 99, 114,	VCC3	Input	+ 3.3 V power supply. Must be connected.
142, 152, 168
18, 36, 66, 67, 86, 109, 127,	VCC5	Input	+ 5 V power supply. Must be connected.
157, 158, 177
1, 13, 29, 31, 41, 46, 55, 57,	VSS	Input	Ground
72, 81, 91, 92, 104, 116,
118, 123, 132, 137, 145,
147, 149, 163, 172, 182
176	BURSTMODE	Input	Burstmode. 0 = Linear, 1 = Interleaved.

MPC2104•MPC2105•MPC2106•MPC2107	MOTOROLA FAST SRAM
6

DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

STANDBY	ADS0	CNTEN0	CWEx	CLKx	Address Used	Operation
H	L	X	X	L±H	N/A	Deselected
L	L	X	L	L±H	External Address	Write Cycle, Begin Burst
L	L	X	H	L±H	External Address	Read Cycle, Begin Burst
X	H	L	L	L±H	Next Address	Write Cycle, Continue Burst
X	H	L	H	L±H	Next Address	Read Cycle, Continue Burst
X	H	H	L	L±H	Current Address	Write Cycle, Suspend Burst
X	H	H	H	L±H	Current Address	Read Cycle, Suspend Burst

NOTES:

1.X means Don't Care.

2.All inputs except COE must meet set±up and hold times for the low±to±high transition of clock (CLK0 ± CLK4).

3.Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation	COE	I/O Status
Read	L	Data Out (DQ0 ± DQ8)
Read	H	High±Z
Write	X	High±Z Ð Data In
Deselected	X	High±Z

NOTES:

1.X means Don't Care.

2.For a write operation following a read operation, COE must be high before the input data required set±up time and held high through the input data hold time.

DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

STANDBY	COE0, COE1	CWE0 ± CWE7	Operation	I/O Status
H	X	X	Deselected	High±Z
L	H	H	Output Disabled	High±Z
L	L	H	Read	Data Out
L	X	L	Write	High±Z

NOTES:

1.X means Don't Care.

2.For a write operation following a read operation, COE0, and COE1 must be high before the input data required set±up time, and held high through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)

Rating		Symbol	Value		Unit
Power Supply Voltage		VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS		Vin, Vout	± 0.5 to VCC + 0.5		V
Output Current (per I/O)	Data RAM	Iout	± 30		mA
	Tag		± 20
Power Dissipation		PD	8.1		W
Temperature Under Bias		Tbias	± 10 to +	85	°C
Operating Temperature		TA	0 to +70		°C
Storage Temperature		Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High±Z at power up.

MOTOROLA FAST SRAM	MPC2104•MPC2105•MPC2106•MPC2107
	7

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)

Parameter	Symbol	Min	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.75	5.25	V
Input High Voltage	VIH	2.2	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

		Parameter		Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)			Data RAM	Ilkg(I)	Ð	± 1.0	μA
			Tag			± 5.0
Output Leakage Current (COE = VIH, Vout = 0 to VCC)			Data RAM	Ilkg(O)	Ð	± 1.0	μA
			Tag			± 5.0
TTL Output Low Voltage (IOL = + 8.0 mA)				VOL	Ð	0.4	V
TTL Output High Voltage (IOH = ± 4.0 mA)				VOH	2.4	Ð	V

POWER SUPPLY CURRENTS

	Parameter			Symbol	Max	Unit
AC Supply Current (COE = VIH, E = VIL, Iout = 0 mA, All Inputs = VIL and VIH,				ICCA		mA
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥	20 ns)	MPC2104			1480
		MPC2105			1420
		MPC2106			2840
		MPC2107			1400
AC Standby Current (E = VIH, Iout = 0 mA, All Inputs = VIL or VIH,				ISB1		mA
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥	20 ns)	MPC2104			620
		MPC2105			700
		MPC2106			1400
		MPC2107			960
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter		Symbol		Typ	Max	Unit
Input Capacitance	(A13 ± A28)	Cin		Ð	15	pF
	(Data RAM Control Pins)			16	20
	(CLK0 ± CLK4)			8	10
	(Tag Control Pins)			Ð	5
Tag Output Capacitance	(MATCH, DIRTYOUT)	Cout		Ð	7	pF
Data RAM Input/Output Capacitance	(DH0 ± DH31, DL0 ± DL31)	CI/O		6	8	pF
Tag Input/Output Capacitance	(A0 ± A11)	CI/O		Ð	7	pF

MPC2104•MPC2105•MPC2106•MPC2107	MOTOROLA FAST SRAM
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