MOTOROLA MC74VHCT573AMEL, MC74VHCT573AML1, MC74VHCT573AML2, MC74VHCT573ADWR2, MC74VHCT573ADTR2 Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D-Type Latch with 3-State Output
The MC74VHCT573A is an advanced high speed CMOS octal latch with 3±state output fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
This 8±bit D±type latch is controlled by a latch enable input and an output enable input. When the output enable input is high, the eight outputs are in a high impedance state.
The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS level output swings.
The VHCT573A input and output (when disabled) structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. These input and output structures help prevent device destruction caused by supply voltage ± input/output voltage mismatch, battery backup, hot insertion, etc.
•High Speed: tPD = 7.7ns (Typ) at VCC = 5V
•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C
•TTL±Compatible Inputs: VIL = 0.8V; VIH = 2.0V
•Power Down Protection Provided on Inputs and Outputs
•Balanced Propagation Delays
•Designed for 4.5V to 5.5V Operating Range
•Low Noise: VOLP = 1.6V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300mA
•ESD Performance: HBM > 2000V; Machine Model > 200V
•Chip Complexity: 234 FETs or 58.5 Equivalent Gates
LOGIC DIAGRAM
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D0 |
2 |
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19 |
Q0 |
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D1 |
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Q1 |
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D2 |
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Q2 |
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DATA |
5 |
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16 |
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NONINVERTING |
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D3 |
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Q3 |
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6 |
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15 |
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INPUTS |
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D4 |
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Q4 |
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OUTPUTS |
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7 |
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14 |
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D5 |
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Q5 |
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8 |
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13 |
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D6 |
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Q6 |
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9 |
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12 |
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D7 |
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Q7 |
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11 |
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LE |
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1 |
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OE |
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MC74VHCT573A
DW SUFFIX
20±LEAD SOIC PACKAGE
CASE 751D±04
DT SUFFIX
20±LEAD TSSOP PACKAGE
CASE 948E±02
M SUFFIX
20±LEAD SOIC EIAJ PACKAGE
CASE 967±01
ORDERING INFORMATION
MC74VHCTXXXADW SOIC
MC74VHCTXXXADT TSSOP
MC74VHCTXXXAM SOIC EIAJ
PIN ASSIGNMENT
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1 |
20 |
VCC |
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OE |
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D0 |
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2 |
19 |
Q0 |
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D1 |
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3 |
18 |
Q1 |
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D2 |
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4 |
17 |
Q2 |
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D3 |
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5 |
16 |
Q3 |
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D4 |
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6 |
15 |
Q4 |
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D5 |
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7 |
14 |
Q5 |
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D6 |
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8 |
13 |
Q6 |
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D7 |
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9 |
12 |
Q7 |
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GND |
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10 |
11 |
LE |
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FUNCTION TABLE
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INPUTS |
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OUTPUT |
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OE |
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LE |
D |
Q |
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L |
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H |
H |
H |
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L |
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H |
L |
L |
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L |
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L |
X |
No Change |
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H |
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X |
X |
Z |
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6/97
Motorola, Inc. 1997 |
1 |
REV 0 |
MC74VHCT573A
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
DC Supply Voltage |
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± 0.5 to + 7.0 |
V |
Vin |
DC Input Voltage |
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± 0.5 to + 7.0 |
V |
Vout |
DC Output Voltage |
Outputs in 3±State |
± 0.5 to + 7.0 |
V |
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High or Low State |
± 0.5 to VCC + 0.5 |
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IIK |
Input Diode Current |
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± 20 |
mA |
IOK |
Output Diode Current (VOUT < GND; VOUT > VCC) |
± 20 |
mA |
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Iout |
DC Output Current, per Pin |
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± 25 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 75 |
mA |
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PD |
Power Dissipation in Still Air, |
SOIC Packages² |
500 |
mW |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
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± 65 to + 150 |
_C |
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.
²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage |
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4.5 |
5.5 |
V |
Vin |
DC Input Voltage |
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0 |
5.5 |
V |
Vout |
DC Output Voltage |
Outputs in 3±State |
0 |
5.5 |
V |
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High or Low State |
0 |
VCC |
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TA |
Operating Temperature |
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± 40 |
+ 85 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC =5.0V ±0.5V |
0 |
20 |
ns/V |
DC ELECTRICAL CHARACTERISTICS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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VCC |
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TA = 25°C |
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TA = ± 40 to 85°C |
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Symbol |
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Parameter |
Test Conditions |
V |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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VIH |
Minimum High±Level |
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4.5 to |
2.0 |
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2.0 |
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V |
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Input Voltage |
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5.5 |
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VIL |
Maximum Low±Level |
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4.5 to |
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0.8 |
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0.8 |
V |
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Input Voltage |
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5.5 |
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VOH |
Minimum High±Level |
IOH = ± 50μA |
4.5 |
4.4 |
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4.5 |
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4.4 |
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V |
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Output Voltage |
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V |
= V |
IH |
or V |
IL |
IOH = ± 8mA |
4.5 |
3.94 |
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3.80 |
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in |
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VOL |
Maximum Low±Level |
IOL = 50μA |
4.5 |
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0.0 |
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0.1 |
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0.1 |
V |
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Output Voltage |
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V |
= V |
IH |
or V |
IL |
IOL = 8mA |
4.5 |
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0.36 |
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0.44 |
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in |
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Iin |
Maximum Input |
Vin = 5.5 V or GND |
0 to 5.5 |
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± 0.1 |
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± 1.0 |
μA |
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Leakage Current |
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IOZ |
Maximum 3±State |
Vin = VIL or VIH |
5.5 |
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± 0.25 |
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± 2.5 |
μA |
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Leakage Current |
Vout = VCC or GND |
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ICC |
Maximum Quiescent |
Vin = VCC or GND |
5.5 |
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4.0 |
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40.0 |
μA |
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Supply Current |
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MOTOROLA |
2 |
VHC Data ± Advanced CMOS Logic |
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DL203 Ð Rev 1 |
MC74VHCT573A
DC ELECTRICAL CHARACTERISTICS
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VCC |
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TA = 25°C |
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TA = ± 40 to 85°C |
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Symbol |
Parameter |
Test Conditions |
V |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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ICCT |
Quiescent Supply |
Per Input: VIN = 3.4V |
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5.5 |
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1.35 |
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1.50 |
mA |
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Current |
Other Input: VCC or GND |
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IOPD |
Output Leakage |
VOUT = 5.5V |
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0 |
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0.5 |
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5.0 |
μA |
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Current |
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
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TA = 25°C |
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TA = ± 40 to 85°C |
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Symbol |
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Parameter |
Test Conditions |
Min |
Typ |
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Max |
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Min |
Max |
Unit |
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tPLH, |
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Maximum Propagation Delay, |
VCC = 5.0 ± 0.5V |
CL = 15pF |
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7.7 |
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12.3 |
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1.0 |
13.5 |
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ns |
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tPHL |
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LE to Q |
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CL = 50pF |
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8.5 |
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13.3 |
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1.0 |
14.5 |
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tPLH, |
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Maximum Propagation Delay, |
VCC = 5.0 ± 0.5V |
CL = 15pF |
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5.1 |
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8.5 |
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1.0 |
9.5 |
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ns |
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tPHL |
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D to Q |
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CL = 50pF |
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5.9 |
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9.5 |
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1.0 |
10.5 |
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tPZL, |
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Output Enable Time, |
VCC = 5.0 ± 0.5V |
CL = 15pF |
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6.3 |
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10.9 |
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1.0 |
12.5 |
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ns |
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tPZH |
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OE to Q |
RL = 1kΩ |
CL = 50pF |
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7.1 |
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11.9 |
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1.0 |
13.5 |
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tPLZ, |
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Output Disable Time, |
VCC = 5.0 ± 0.5V |
CL = 50pF |
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8.8 |
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11.2 |
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1.0 |
12.0 |
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ns |
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tPHZ |
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OE to Q |
RL = 1kΩ |
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tOSLH, |
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Output to Output Skew |
VCC = 5.5 ± 0.5V |
CL = 50pF |
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1.0 |
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1.0 |
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ns |
tOSHL |
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(Note 1.) |
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Cin |
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Maximum Input Capacitance |
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4 |
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10 |
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10 |
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pF |
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Cout |
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Maximum Three±State Output |
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6 |
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pF |
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Capacitance (Output in |
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High±Impedance State) |
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Typical @ 25°C, VCC = 5.0V |
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CPD |
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Power Dissipation Capacitance (Note 2.) |
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25 |
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pF |
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1.Parameter guaranteed by design. tOSLH = |tPLHm ± tPLHn|, tOSHL = |tPHLm ± tPHLn|.
2.CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Averageoperatingcurrentcanbeobtainedbytheequation:ICC(OPR) = CPD VCC fin+ ICC / 8(perlatch).CPDisusedtodeterminetheno±load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50 pF, VCC = 5.0V)
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TA = 25°C |
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Symbol |
Parameter |
Typ |
Max |
Unit |
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VOLP |
Quiet Output Maximum Dynamic VOL |
1.2 |
1.6 |
V |
VOLV |
Quiet Output Minimum Dynamic VOL |
±1.2 |
±1.6 |
V |
VIHD |
Minimum High Level Dynamic Input Voltage |
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2.0 |
V |
VILD |
Maximum Low Level Dynamic Input Voltage |
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0.8 |
V |
TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
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TA = ± 40 |
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TA = 25°C |
to 85°C |
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Symbol |
Parameter |
Test Conditions |
Typ |
Limit |
Limit |
Unit |
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tw(h) |
Minimum Pulse Width, LE |
VCC = 5.0 |
±0.5V |
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6.5 |
8.5 |
ns |
tsu |
Minimum Setup Time, D to LE |
VCC = 5.0 |
± 0.5V |
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1.5 |
1.5 |
ns |
th |
Minimum Hold Time, D to LE |
VCC = 5.0 |
± 0.5V |
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3.5 |
3.5 |
ns |
VHC Data ± Advanced CMOS Logic |
3 |
MOTOROLA |
DL203 Ð Rev 1 |
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