MOTOROLA MC74VHCT138AD, MC74VHCT138ADR2, MC74VHCT138AM, MC74VHCT138AMEL, MC74VHCT138AML1 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3-to-8 Line Decoder

The MC74VHCT138A is an advanced high speed CMOS 3±to±8 decoder fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

When the device is enabled, three Binary Select inputs (A0 ± A2) determine which one of the outputs (Y0 ± Y7) will go Low. When enable input E3 is held Low or either E2 or E1 is held High, decoding function is inhibited and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade connection and for use as an address decoder for memory systems.

The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3V to 5.0V, because they have full 5V CMOS level output swings.

The VHCT138A input structures provide protection when voltages between 0V and 5.5V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage

± input/output voltage mismatch, battery backup, hot insertion, etc.

•High Speed: tPD = 7.6ns (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•TTL±Compatible Inputs: VIL = 0.8V; VIH = 2.0V

•Power Down Protection Provided on Inputs and Outputs

•Balanced Propagation Delays

•Designed for 4.5V to 5.5V Operating Range

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 122 FETs or 30.5 Equivalent Gates

FUNCTION TABLE

MC74VHCT138A

D SUFFIX

16±LEAD SOIC PACKAGE

CASE 751B±05

DT SUFFIX

16±LEAD TSSOP PACKAGE

CASE 948F±01

M SUFFIX

16±LEAD SOIC EIAJ PACKAGE

CASE 966±01

ORDERING INFORMATION

MC74VHCTXXXAD SOIC MC74VHCTXXXADT TSSOP MC74VHCTXXXAM SOIC EIAJ

PIN ASSIGNMENT

	A0			1	16		VCC
	A1			2	15
							Y0
				3	14
	A2						Y1
				4
	E1				13		Y2
				5	12
	E2						Y3
				6	11
	E3						Y4
				7	10
	Y7						Y5
GND				8	9		Y6

Inputs

Outputs

15

A0

1

14

Y0

E3

E2

E1

A2 A1 A0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

SELECT

Y1

2

13

Y2

X

X

H

X

X

X

H

H

H

H

H

H

H

H

A1

INPUTS

12

ACTIVE±LOW

X

H

X

X

X

X

H

H

H

H

H

H

H

H

A2

3

Y3

L

X

X

X

X

X

H

H

H

H

H

H

H

H

11

OUTPUTS

Y4

H L L

L L L

L H

H H H H H H

10

Y5

H L L

L L H

H L H H H H H H

9 Y6

H L L

L H L

H H L H H H H H

7

H L L

L H H

H H H L H H H H

Y7

H L L

H L L

H H H H L H H H

ENABLE

E3

6

H L L

H L H

H H H H H L H H

5

LOGIC DIAGRAM

INPUTS

E2

H L L

H H L

H H H H H H L H

4

H L L

H H H

H H H H H H H L

E1

H = high level (steady state); L = low level (steady state); X = don't care

6/97

Motorola, Inc. 1997

1

REV 0

MC74VHCT138A

		EXPANDED LOGIC DIAGRAM
		15	Y0
		14	Y1
A0	1	13	Y2
A1	2	12	Y3
	3	11	Y4
A2
		10	Y5
E2	5
E1	4	9	Y6
		7	Y7
E3	6

MOTOROLA	2	VHC Data ± Advanced CMOS Logic
		DL203 Ð Rev 1