MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D-Type Flip-Flop with Set and Reset
The MC74VHC74 is an advanced high speed CMOS D±type flip±flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.
•High Speed: fmax = 170MHz (Typ) at VCC = 5V
•Low Power Dissipation: ICC = 2μA (Max) at TA = 25°C
•High Noise Immunity: VNIH = VNIL = 28% VCC
•Power Down Protection Provided on Inputs
•Balanced Propagation Delays
•Designed for 2V to 5.5V Operating Range
•Low Noise: VOLP = 0.8V (Max)
•Pin and Function Compatible with Other Standard Logic Families
•Latchup Performance Exceeds 300mA
•ESD Performance: HBM > 2000V; Machine Model > 200V
•Chip Complexity: 128 FETs or 32 Equivalent Gates
LOGIC DIAGRAM
RD1 |
1 |
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RD2 |
13 |
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D1 |
2 |
5 |
Q1 |
D2 |
12 |
9 |
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Q2 |
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CP1 |
3 |
6 |
Q1 |
CP2 |
11 |
8 |
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Q2 |
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SD1 |
4 |
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SD2 |
10 |
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FUNCTION TABLE
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Inputs |
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Outputs |
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SD |
RD |
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CP |
D |
Q |
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Q |
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L |
H |
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X |
X |
H |
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L |
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H |
L |
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X |
X |
L |
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H |
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L |
L |
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X |
X |
H* |
H* |
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H |
H |
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H |
H |
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L |
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H |
H |
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L |
L |
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H |
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H |
H |
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L |
X |
No Change |
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H |
H |
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H |
X |
No Change |
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H |
H |
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X |
No Change |
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MC74VHC74
D SUFFIX
14±LEAD SOIC PACKAGE
CASE 751A±03
DT SUFFIX
14±LEAD TSSOP PACKAGE
CASE 948G±01
M SUFFIX
14±LEAD SOIC EIAJ PACKAGE
CASE 965±01
ORDERING INFORMATION
MC74VHCXXD SOIC MC74VHCXXDT TSSOP MC74VHCXXM SOIC EIAJ
PIN ASSIGNMENT
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1 |
14 |
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VCC |
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RD1 |
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D1 |
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2 |
13 |
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RD2 |
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CP1 |
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3 |
12 |
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D2 |
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4 |
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SD1 |
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11 |
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CP2 |
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Q1 |
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5 |
10 |
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SD2 |
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6 |
9 |
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Q1 |
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Q2 |
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7 |
8 |
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GND |
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Q2 |
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*Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
6/97
Motorola, Inc. 1997 |
1 |
REV 1 |
MC74VHC74
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
DC Supply Voltage |
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± 0.5 to + 7.0 |
V |
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Vin |
DC Input Voltage |
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± 0.5 to + 7.0 |
V |
Vout |
DC Output Voltage |
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± 0.5 to VCC + 0.5 |
V |
IIK |
Input Diode Current |
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± 20 |
mA |
IOK |
Output Diode Current |
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± 20 |
mA |
Iout |
DC Output Current, per Pin |
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± 25 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
± 50 |
mA |
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PD |
Power Dissipation in Still Air, |
SOIC Packages² |
500 |
mW |
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TSSOP Package² |
450 |
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Tstg |
Storage Temperature |
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± 65 to + 150 |
_C |
*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.
²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage |
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2.0 |
5.5 |
V |
Vin |
DC Input Voltage |
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0 |
5.5 |
V |
Vout |
DC Output Voltage |
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0 |
VCC |
V |
TA |
Operating Temperature, All Package Types |
± 40 |
+ 85 |
_C |
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tr, tf |
Input Rise and Fall Time |
VCC = 3.3V ±0.3V |
0 |
100 |
ns/V |
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VCC =5.0V ±0.5V |
0 |
20 |
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DC ELECTRICAL CHARACTERISTICS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the
range GND v (Vin or Vout) v VCC. Unused inputs must always be
tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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VCC |
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TA = 25°C |
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TA = ± 40 to 85°C |
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Symbol |
Parameter |
Test Conditions |
V |
Min |
Typ |
Max |
Min |
Max |
Unit |
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VIH |
Minimum High±Level |
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2.0 |
1.50 |
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1.50 |
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V |
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Input Voltage |
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3.0 to |
VCC x 0.7 |
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VCC x 0.7 |
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5.5 |
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VIL |
Maximum Low±Level |
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2.0 |
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0.50 |
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0.50 |
V |
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Input Voltage |
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3.0 to |
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VCC x 0.3 |
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VCC x 0.3 |
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5.5 |
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VOH |
Minimum High±Level |
Vin = VIH or VIL |
2.0 |
1.9 |
2.0 |
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1.9 |
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V |
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Output Voltage |
IOH = ± 50μA |
3.0 |
2.9 |
3.0 |
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2.9 |
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4.5 |
4.4 |
4.5 |
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4.4 |
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Vin = VIH or VIL |
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IOH = ± 4mA |
3.0 |
2.58 |
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2.48 |
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IOH = ± 8mA |
4.5 |
3.94 |
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3.80 |
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VOL |
Maximum Low±Level |
Vin = VIH or VIL |
2.0 |
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0.0 |
0.1 |
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0.1 |
V |
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Output Voltage |
IOL = 50μA |
3.0 |
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0.0 |
0.1 |
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0.1 |
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4.5 |
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0.0 |
0.1 |
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0.1 |
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Vin = VIH or VIL |
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IOL = 4mA |
3.0 |
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0.36 |
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0.44 |
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IOL = 8mA |
4.5 |
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0.36 |
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0.44 |
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MOTOROLA |
2 |
VHC Data ± Advanced CMOS Logic |
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DL203 Ð Rev 1 |