MOTOROLA MC74VHC595ML2, MC74VHC595M, MC74VHC595D, MC74VHC595DR2, MC74VHC595DT Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

8-Bit Shift Register with Output Storage Register

(3-State)

The MC74VHC595 is an advanced high speed 8±bit shift register with an output storage register fabricated with silicon gate CMOS technology.

It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

The MC74VHC595 contains an 8±bit static shift register which feeds an 8±bit storage register.

Shift operation is accomplished on the positive going transition of the Shift Clock input (SCK). The output register is loaded with the contents of the shift register on the positive going transition of the Register Clock input (RCK). Since the RCK and SCK signals are independent, parallel outputs can be held stable during the shift operation. And, since the parallel outputs are 3±state, the VHC595 can be directly connected to an 8±bit bus. This register can be used in serial±to±parallel conversion, data receivers, etc.

The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

•High Speed: fmax = 185MHz (Typ) at VCC = 5V

•Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2V to 5.5V Operating Range

•Low Noise: VOLP = 1.0V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300mA

•ESD Performance: HBM > 2000V; Machine Model > 200V

•Chip Complexity: 328 FETs or 82 Equivalent Gates

		LOGIC DIAGRAM
SERIAL		14		15
DATA	SI				QA
INPUT				1	QB
				2	QC
				3	QD	PARALLEL
		SHIFT	STORAGE	4	QE	DATA
						OUTPUTS
		REGISTER	REGISTER	5
					QF
				6
					QG
				7	QH
	SCK	11
		10		9	SQH	SERIAL
SCLR						DATA
		12				OUTPUT
	RCK
	OE	13

MC74VHC595

D SUFFIX

16±LEAD SOIC PACKAGE

CASE 751B±05

DT SUFFIX

16±LEAD TSSOP PACKAGE

CASE 948F±01

M SUFFIX

16±LEAD SOIC EIAJ PACKAGE

CASE 966±01

ORDERING INFORMATION

MC74VHCXXXD SOIC MC74VHCXXXDT TSSOP MC74VHCXXXM SOIC EIAJ

PIN ASSIGNMENT

QB		1	16		VCC
QC		2	15		QA
QD		3	14		SI
QE
		4	13		OE
QF		5	12		RCK
QG		6	11		SCK
QH
		7	10		SCLR
GND		8	9		SQH

6/97

Motorola, Inc. 1997

1

REV 1

MC74VHC595

FUNCTION TABLE

			Inputs					Resulting Function
		Serial	Shift	Reg	Output		Shift	Storage	Serial	Parallel
	Reset	Input	Clock	Clock	Enable		Register	Register	Output	Outputs
Operation	(SCLR)	(SI)	(SCK)	(RCK)	(OE)		Contents	Contents	(SQH)	(QA ± QH)
Clear shift register	L	X	X	L, H, ↓	L		L	U	L	U
Shift data into shift register	H	D	↑	L, H, ↓	L		D→ SRA;	U	SRG→ SRH	U
						SRN→ SRN+1
Registers remains	H	X	L, H, ↓	X	L		U	**	U	**
unchanged
Transfer shift register	H	X	L, H, ↓	↑	L		U	SRN³STRN	*	SRN
contents to storage register
Storage register remains	X	X	X	L, H, ↓	L		*	U	*	U
unachanged
Enable parallel outputs	X	X	X	X	L		*	**	*	Enabled
Force outputs into high	X	X	X	X	H		*	**	*	Z
impedance state
SR = shift register contents	D = data (L, H) logic level			↓ = High±to±Low			* = depends on Reset and Shift Clock inputs
STR = storage register contents U = remains unchanged				↑ = Low±to±High			** = depends on Register Clock input

MAXIMUM RATINGS*

	Symbol	Parameter		Value	Unit
	VCC	DC Supply Voltage		± 0.5 to + 7.0	V
	Vin	DC Input Voltage		± 0.5 to + 7.0	V
	Vout	DC Output Voltage		± 0.5 to VCC + 0.5	V
	IIK	Input Diode Current		± 20	mA
	IOK	Output Diode Current		± 20	mA
	Iout	DC Output Current, per Pin		± 25	mA
	ICC	DC Supply Current, VCC and GND Pins		± 50	mA
	PD	Power Dissipation in Still Air,	SOIC Packages²	500	mW
			TSSOP Package²	450
	Tstg	Storage Temperature		± 65 to + 150	_C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute±maximum±rated conditions is not implied.

²Derating Ð SOIC Packages: ± 7 mW/ _C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter		Min	Max	Unit
VCC	DC Supply Voltage		2.0	5.5	V
Vin	DC Input Voltage		0	5.5	V
Vout	DC Output Voltage		0	VCC	V
TA	Operating Temperature, All Package Types		± 40	+ 85	_C
tr, tf	Input Rise and Fall Time	VCC = 3.3V ±0.3V	0	100	ns/V
		VCC =5.0V ±0.5V	0	20

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MOTOROLA	2	VHC Data ± Advanced CMOS Logic
		DL203 Ð Rev 1

MC74VHC595

DC ELECTRICAL CHARACTERISTICS

			VCC		TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions	V	Min	Typ	Max	Min	Max	Unit
VIH	Minimum High±Level		2.0	1.50			1.50		V
	Input Voltage		3.0 to	VCC x 0.7			VCC x 0.7
			5.5
VIL	Maximum Low±Level		2.0			0.50		0.50	V
	Input Voltage		3.0 to			VCC x 0.3		VCC x 0.3
			5.5
VOH	Minimum High±Level	Vin = VIH or VIL	2.0	1.9	2.0		1.9		V
	Output Voltage	IOH = ± 50μA	3.0	2.9	3.0		2.9
			4.5	4.4	4.5		4.4
		Vin = VIH or VIL
		IOH = ± 4mA	3.0	2.58			2.48
		IOH = ± 8mA	4.5	3.94			3.80
VOL	Maximum Low±Level	Vin = VIH or VIL	2.0		0.0	0.1		0.1	V
	Output Voltage	IOL = 50μA	3.0		0.0	0.1		0.1
			4.5		0.0	0.1		0.1
		Vin = VIH or VIL
		IOL = 4mA	3.0			0.36		0.44
		IOL = 8mA	4.5			0.36		0.44
IOZ	Three±State Output	Vin = VIH or VIL	5.5			± 0.25		± 2.50	μA
	Off±State Current	Vout = VCC or GND
Iin	Maximum Input	Vin = 5.5V or GND	0 to 5.5			± 0.1		± 1.0	μA
	Leakage Current
ICC	Maximum Quiescent	Vin = VCC or GND	5.5			4.0		40.0	μA
	Supply Current

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)

					TA = 25°C		TA = ± 40 to 85°C
Symbol	Parameter	Test Conditions		Min	Typ	Max	Min	Max	Unit
fmax	Maximum Clock Frequency	VCC = 3.3 ± 0.3V	CL = 15pF	80	150		70		MHz
	(50% Duty Cycle)	RL = 1kΩ	CL = 50pF	55	130		50
		VCC = 5.0 ± 0.5V	CL = 15pF	135	185		115
		RL = 1kΩ	CL = 50pF	95	155		85
tPLH,	Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		8.8	13.0	1.0	15.0	ns
tPHL	SCK to SQH		CL = 50pF		11.3	16.5	1.0	18.5
		VCC = 5.0 ± 0.5V	CL = 15pF		6.2	8.2	1.0	9.4
			CL = 50pF		7.7	10.2	1.0	11.4
tPHL	Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		8.4	12.8	1.0	13.7	ns
	SCLR to SQH		CL = 50pF		10.9	16.3	1.0	17.2
		VCC = 5.0 ± 0.5V	CL = 15pF		5.9	8.0	1.0	9.1
			CL = 50pF		7.4	10.0	1.0	11.1
tPLH,	Propagation Delay,	VCC = 3.3 ± 0.3V	CL = 15pF		7.7	11.9	1.0	13.5	ns
tPHL	RCK to QA ± QH		CL = 50pF		10.2	15.4	1.0	17.0
		VCC = 5.0 ± 0.5V	CL = 15pF		5.4	7.4	1.0	8.5
			CL = 50pF		6.9	9.4	1.0	10.5
tPZL,	Output Enable Time,	VCC = 3.3 ± 0.3V	CL = 15pF		7.5	11.5	1.0	13.5	ns
tPZH	OE to QA ± QH	RL = 1kΩ	CL = 50pF		9.0	15.0	1.0	17.0
		VCC = 5.0 ± 0.5V	CL = 15pF		4.8	8.6	1.0	10.0
		RL = 1kΩ	CL = 50pF		8.3	10.6	1.0	12.0

VHC Data ± Advanced CMOS Logic	3	MOTOROLA
DL203 Ð Rev 1