Motorola MC54HC4051A, MC54HC4052A, MC74HC4053AN, MC74HC4051ADW, MC74HC4051ADT Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Information

MC54/74HC4051A

Analog

Multiplexers/

MC74HC4052A

Demultiplexers

MC54/74HC4053A

High±Performance Silicon±Gate CMOS

The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize

silicon±gate CMOS technology to achieve fast propagation delays, low ON

resistances, and low OFF leakage currents. These analog multiplexers/

J SUFFIX

demultiplexers control analog voltages that may vary across the complete

CERAMIC PACKAGE

power supply range (from VCC to VEE).

CASE 620±10

The HC4051A, HC4052A and HC4053A are identical in pinout to the

metal±gate MC14051AB, MC14052AB and MC14053AB. The Channel±Se-

N SUFFIX

lect inputs determine which one of the Analog Inputs/Outputs is to be

PLASTIC PACKAGE

connected, by means of an analog switch, to the Common Output/Input.

CASE 648±08

When the Enable pin is HIGH, all analog switches are turned off.

D SUFFIX

The Channel±Select and Enable inputs are compatible with standard

CMOS outputs; with pullup resistors they are compatible with LSTTL

SOIC PACKAGE

outputs.

CASE 751B±05

These devices have been designed so that the ON resistance (Ron) is

DW SUFFIX

more linear over input voltage than Ron of metal±gate CMOS analog

SOIC WIDE PACKAGE

switches.

CASE 751G±02

For a multiplexer/demultiplexer with channel±select latches, see

HC4351A.

DT SUFFIX

• Fast Switching and Propagation Speeds

TSSOP PACKAGE

• Low Crosstalk Between Switches

CASE 948F±01

• Diode Protection on All Inputs/Outputs

ORDERING INFORMATION

• Analog Power Supply Range (VCC ± VEE) = 2.0 to 12.0 V

MC54HCXXXXAJ

Ceramic

• Digital (Control) Power Supply Range (VCC ± GND) = 2.0 to 6.0 V

MC74HCXXXXAN

Plastic

• Improved Linearity and Lower ON Resistance Than Metal±Gate

MC74HCXXXXAD

SOIC

Counterparts

MC74HCXXXXADW

SOIC Wide

• Low Noise

MC74HCXXXXADT

TSSOP

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A Ð 184 FETs or 46 Equivalent Gates

FUNCTION TABLE ± MC54/74HC4051A

HC4052A Ð 168 FETs or 42 Equivalent Gates

Control Inputs

HC4053A Ð 156 FETs or 39 Equivalent Gates

Select

LOGIC DIAGRAM

Enable

ON Channels

MC54/74HC4051A

Single±Pole, 8±Position Plus Common Off

X0 13

X1 14

X COMMON

X2 15

ANALOG

MULTIPLEXER/

OUTPUT/

INPUTS/

INPUT

OUTPUTS

DEMULTIPLEXER

NONE

Pinout: MC54/74HC4051A (Top View)

X = Don't Care

VCC

X7 4

CHANNEL

A 11

SELECT

INPUTS

ENABLE

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

Enable

VEE

GND

This document contains information on a new product. Specifications and information herein are subject to

change without notice.

10/97

Motorola, Inc. 1997

REV 0

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

LOGIC DIAGRAM

MC74HC4052A Double±Pole, 4±Position Plus Common Off

	X0	12
	X1	14	X SWITCH
	X2	15	X SWITCH
	X2	15
ANALOG	X3	11
ANALOG
INPUTS/OUTPUTS	Y0	1
	Y1	5	Y SWITCH
	Y2	2	Y SWITCH
	Y2	2
	Y3	4
CHANNEL-SELECT	A 10
CHANNEL-SELECT		9
INPUTS	B	9
ENABLE		6

13 X

COMMON

OUTPUTS/INPUTS

3 Y

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

FUNCTION TABLE ± MC74HC4052A

Control Inputs

	Select
Enable	B	A	ON Channels

L	L	L	Y0	X0
L	L	H	Y1	X1
L	H	L	Y2	X2
L	H	H	Y3	X3
H	X	X		NONE

X = Don't Care

Pinout: MC74HC4052A (Top View)

VCC		X2	X1	X	X0	X3	A	B
	16	15	14	13	12	11	10	9


1	2	3	4	5		6	7		8
Y0	Y2	Y	Y3	Y1	Enable		VEE	GND

LOGIC DIAGRAM

MC54/74HC4053A

Triple Single±Pole, Double±Position Plus Common Off

	X0	12	X SWITCH
	X1	13	X SWITCH
ANALOG	Y0	2	Y SWITCH
ANALOG		1	Y SWITCH
INPUTS/OUTPUTS Y1
	Z0	5	Z SWITCH
	Z1	3	Z SWITCH
	A 11
CHANNEL-SELECT	B	10
INPUTS	B	9
INPUTS	C
	C
ENABLE		6

14X

15Y COMMON OUTPUTS/INPUTS

4 Z

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

NOTE: This device allows independent control of each switch. Channel±Select Input A controls the X±Switch, Input B controls the Y±Switch and Input C controls the Z±Switch

FUNCTION TABLE ± MC54/74HC4053A

Control Inputs

		Select
Enable	C	B	A	ON Channels

L	L	L	L	Z0	Y0	X0
L	L	L	H	Z0	Y0	X1
L	L	H	L	Z0	Y1	X0
L	L	H	H	Z0	Y1	X1
L	H	L	L	Z1	Y0	X0
L	H	L	H	Z1	Y0	X1
L	H	H	L	Z1	Y1	X0
L	H	H	H	Z1	Y1	X1
H	X	X	X		NONE

X = Don't Care

Pinout: MC54/74HC4053A (Top View)

VCC		Y		X		X1		X0		A		B		C
16		15		14		13		12		11		10		9




1	2	3	4	5		6	7		8
Y1	Y0	Z1	Z	Z0	Enable		VEE	GND

MOTOROLA	2	High±Speed CMOS Logic Data
		DL129 Ð Rev 6

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

MAXIMUM RATINGS*

Symbol	Parameter		Value	Unit

VCC	Positive DC Supply Voltage	(Referenced to GND)	± 0.5 to + 7.0	V
VCC	Positive DC Supply Voltage	(Referenced to GND)	± 0.5 to + 7.0	V
		(Referenced to VEE)	± 0.5 to + 14.0
VEE	Negative DC Supply Voltage (Referenced to GND)		± 7.0 to + 5.0	V
VIS	Analog Input Voltage		VEE ± 0.5 to	V
			VCC + 0.5
Vin	Digital Input Voltage (Referenced to GND)		± 0.5 to VCC + 0.5	V
I	DC Current, Into or Out of Any Pin		± 25	mA

PD	Power Dissipation in Still Air,	Plastic or Ceramic DIP²	750	mW
		SOIC Package²	500
		TSSOP Package²	450

Tstg	Storage Temperature Range		± 65 to + 150	_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
TL	Lead Temperature, 1 mm from Case for 10 Seconds			_C
	Plastic DIP, SOIC or TSSOP Package		260
		Ceramic DIP	300

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, Vin and Vout should be constrained to the

range GND v (Vin or Vout) v VCC. Unused inputs must always be

tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.

²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C TSSOP Package: ± 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol	Parameter			Min	Max	Unit

VCC	Positive DC Supply Voltage	(Referenced to GND)		2.0	6.0	V
		(Referenced to VEE)		2.0	12.0
VEE	Negative DC Supply Voltage, Output (Referenced to			± 6.0	GND	V
	GND)

VIS	Analog Input Voltage			VEE	VCC	V
Vin	Digital Input Voltage (Referenced to GND)			GND	VCC	V
VIO*	Static or Dynamic Voltage Across Switch				1.2	V
TA	Operating Temperature Range, All Package Types			± 55	+ 125	_C
tr, tf	Input Rise/Fall Time		VCC = 2.0 V	0	1000	ns
	(Channel Select or Enable Inputs)		VCC = 3.0 V	0	600
			VCC = 4.5 V	0	500
			VCC = 6.0 V	0	400

*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

High±Speed CMOS Logic Data	3	MOTOROLA
DL129 Ð Rev 6

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

DC CHARACTERISTICS Ð Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted

				VCC	Guaranteed Limit
				VCC
Symbol	Parameter	Condition		V	±55 to 25°C	≤85°C	≤125°C		Unit

VIH	Minimum High±Level Input Voltage,	Ron = Per Spec		2.0	1.50	1.50		1.50	V
	Channel±Select or Enable Inputs			3.0	2.10	2.10		2.10
				4.5	3.15	3.15		3.15
				6.0	4.20	4.20		4.20

VIL	Maximum Low±Level Input Voltage,	Ron = Per Spec		2.0	0.5	0.5		0.5	V
	Channel±Select or Enable Inputs			3.0	0.9	0.9		0.9
				4.5	1.35	1.35		1.35
				6.0	1.8	1.8		1.8

Iin	Maximum Input Leakage Current,	Vin = VCC or GND,		6.0	± 0.1	± 1.0		± 1.0	μA
	Channel±Select or Enable Inputs	VEE = ± 6.0 V
ICC	Maximum Quiescent Supply	Channel Select, Enable and							μA
	Current (per Package)	VIS = VCC or GND;	VEE = GND	6.0	1	10		20
		VIO = 0 V	VEE = ± 6.0	6.0	4	40		80

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

DC CHARACTERISTICS Ð Analog Section

							Guaranteed Limit

Symbol	Parameter		Condition		VCC	VEE	±55 to 25°C	≤85°C	≤125°C	Unit
Ron	Maximum ªONº Resistance		Vin = VIL or VIH; VIS = VCC to		4.5	0.0	190	240	280	Ω
			VEE; IS ≤ 2.0 mA		4.5	± 4.5	120	150	170
			(Figures 1, 2)		6.0	± 6.0	100	125	140

			Vin = VIL or VIH; VIS	= VCC or	4.5	0.0	150	190	230
			VEE (Endpoints); IS	≤ 2.0 mA	4.5	± 4.5	100	125	140
			(Figures 1, 2)		6.0	± 6.0	80	100	115

Ron	Maximum Difference in ªONº		Vin = VIL or VIH;		4.5	0.0	30	35	40	Ω
	Resistance Between Any Two		VIS = 1/2 (VCC ± VEE);		4.5	± 4.5	12	15	18
	Channels in the Same Package		IS ≤ 2.0 mA		6.0	± 6.0	10	12	14
Ioff	Maximum Off±Channel Leakage		Vin = VIL or VIH;							μA
	Current, Any One Channel		VIO = VCC ± VEE;		6.0	± 6.0	0.1	0.5	1.0
			Switch Off (Figure 3)

	Maximum Off±Channel HC4051A		Vin = VIL or VIH;		6.0	± 6.0	0.2	2.0	4.0
	Leakage Current,	HC4052A	VIO = VCC ± VEE;		6.0	± 6.0	0.1	1.0	2.0
	Common Channel	HC4053A	Switch Off (Figure 4)		6.0	± 6.0	0.1	1.0	2.0

Ion	Maximum On±Channel HC4051A		Vin = VIL or VIH;		6.0	± 6.0	0.2	2.0	4.0	μA
	Leakage Current,	HC4052A	Switch±to±Switch =		6.0	± 6.0	0.1	1.0	2.0
	Channel±to±Channel	HC4053A	VCC ± VEE; (Figure 5)		6.0	± 6.0	0.1	1.0	2.0

MOTOROLA	4	High±Speed CMOS Logic Data
		DL129 Ð Rev 6

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

			VCC	Guaranteed Limit
			VCC
Symbol		Parameter	V	±55 to 25°C	≤85°C	≤125°C	Unit

tPLH,	Maximum Propagation Delay, Channel±Select to Analog Output		2.0	370	465	550	ns
tPHL	(Figure 9)		4.5	74	93	110
			6.0	63	79	94

tPLH,	Maximum Propagation Delay, Analog Input to Analog Output		2.0	60	75	90	ns
tPHL	(Figure 10)		4.5	12	15	18
			6.0	10	13	15

tPLZ,	Maximum Propagation Delay, Enable to Analog Output		2.0	290	364	430	ns
tPHZ	(Figure 11)		4.5	58	73	86
			6.0	49	62	73

tPZL,	Maximum Propagation Delay, Enable to Analog Output		2.0	345	435	515	ns
tPZH	(Figure 11)		4.5	69	87	103
			6.0	59	74	87

Cin	Maximum Input Capacitance, Channel±Select or Enable Inputs			10	10	10	pF
CI/O	Maximum Capacitance	Analog I/O		35	35	35	pF
	(All Switches Off)	Common O/I: HC4051A		130	130	130
		HC4052A		80	80	80
		HC4053A		50	50	50

		Feedthrough		1.0	1.0	1.0

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High± Speed CMOS Data Book (DL129/D).

			Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD	Power Dissipation Capacitance (Figure 13)*	HC4051A	45	pF
		HC4052A	80
		HC4053A	45

*Used to determine the no±load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).

High±Speed CMOS Logic Data	5	MOTOROLA
DL129 Ð Rev 6

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