MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex Buffers/Logic-Level
Down Converters
High±Performance Silicon±Gate CMOS
The MC54/74HC4049 consists of six inverting buffers, and the MC54/74HC4050 consists of six noninverting buffers. They are identical in pinout to the MC14049UB and MC14050B metal±gate CMOS buffers. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The input protection circuitry on these devices has been modified by eliminating the VCC diodes to allow the use of input voltages up to 15 volts. Thus, the devices may be used as logic±level translators that convert from a high voltage to a low voltage while operating at the low±voltage power supply. They allow MC14000±series CMOS operating up to 15 volts to be interfaced with High±Speed CMOS at 2 to 6 volts. The protection diodes to GND are Zener diodes, which protect the inputs from both positive and negative voltage transients.
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2 to 6 V
•Low Input Current: 5 μA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the Requirements Defined by JEDEC Standard No. 7A
•Chip Complexity: 36 FETs or 9 Equivalent Gates (4049)
24 FETs or 6 Equivalent Gates (4050)
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LOGIC DIAGRAMS |
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HC4049 |
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HC4050 |
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(INVERTING BUFFER) |
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(NONINVERTING BUFFER) |
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2 |
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3 |
2 |
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A0 |
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Y0 |
A0 |
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Y0 |
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4 |
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4 |
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5 |
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A1 |
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Y1 |
A1 |
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Y1 |
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7 |
6 |
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7 |
6 |
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A2 |
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Y2 |
A2 |
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Y2 |
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9 |
10 |
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9 |
10 |
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A3 |
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Y3 |
A3 |
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Y3 |
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11 |
12 |
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11 |
12 |
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A4 |
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Y4 |
A4 |
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Y4 |
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14 |
15 |
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14 |
15 |
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A5 |
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Y5 |
A5 |
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Y5 |
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PIN 1 = VCC
PIN 8 = GND
PINS 13, 16 = NO CONNECTION
MC54/74HC4049
MC54/74HC4050
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J SUFFIX |
16 |
CERAMIC PACKAGE |
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CASE 620±10 |
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1 |
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N SUFFIX |
16 |
PLASTIC PACKAGE |
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CASE 648±08 |
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1 |
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D SUFFIX |
16 |
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SOIC PACKAGE |
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1 |
CASE 751B±05 |
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ORDERING INFORMATION |
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MC54HCXXXXJ |
Ceramic |
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MC74HCXXXXN |
Plastic |
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MC74HCXXXXD |
SOIC |
PIN ASSIGNMENT
VCC |
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1 |
16 |
NC |
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Y0 |
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2 |
15 |
Y5 |
A0 |
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3 |
14 |
A5 |
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Y1 |
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4 |
13 |
NC |
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A1 |
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5 |
12 |
Y4 |
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Y2 |
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6 |
11 |
A4 |
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A2 |
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7 |
10 |
Y3 |
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GND |
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8 |
9 |
A3 |
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NC = NO CONNECTION
FUNCTION TABLE
A |
Y Outputs |
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Input |
HC4049 |
HC4060 |
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L |
H |
L |
H |
L |
H |
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10/95
Motorola, Inc. 1995 |
REV 6 |
MC54/74HC4049 MC54/74HC4050
MAXIMUM RATINGS*
Symbol |
Parameter |
Value |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
± 0.5 to + 7.0 |
V |
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Vin |
DC Input Voltage (Referenced to GND) |
± 1.5 to + 18 |
V |
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Vout |
DC Output Voltage (Referenced to GND) |
± 0.5 to VCC + 0.5 |
V |
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Iin |
DC Input Current, per Pin |
± 20 |
mA |
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Iout |
DC Output Current, per Pin |
± 25 |
mA |
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ICC |
DC Supply Current, VCC and GND Pins |
± 50 |
mA |
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PD |
Power Dissipation in Still Air, Plastic or Ceramic DIP² |
750 |
mW |
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SOIC Package² |
500 |
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Tstg |
Storage Temperature |
± 65 to + 150 |
_C |
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TL |
Lead Temperature, 1 mm from Case for 10 Seconds |
260 |
_C |
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(Plastic DIP or SOIC Package) |
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(Ceramic DIP) |
300 |
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This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the GND pin, only. Extra precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high±impedance circuit. For proper operation, the ranges GND v Vin v 15 V and
GND v Vout v VCC are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions.
²Derating Ð Plastic DIP: ± 10 mW/ _C from 65_ to 125_C Ceramic DIP: ± 10 mW/_C from 100_ to 125_C SOIC Package: ± 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol |
Parameter |
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Min |
Max |
Unit |
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VCC |
DC Supply Voltage (Referenced to GND) |
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2.0 |
6.0 |
V |
Vin |
DC Input Voltage (Referenced to GND) |
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0 |
VCC |
V |
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to 15 |
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Vout |
DC Output Voltage (Referenced to GND) |
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0 |
VCC |
V |
TA |
Operating Temperature, All Package Types |
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± 55 |
+ 125 |
_C |
tr, tf |
Input Rise and Fall Time |
VCC = 2.0 V |
0 |
1000 |
ns |
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(Figure 1) |
VCC = 4.5 V |
0 |
500 |
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VCC = 6.0 V |
0 |
400 |
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
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Guaranteed Limit |
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VCC |
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± 55 to |
v _ |
v |
_ |
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Symbol |
Parameter |
Test Conditions |
V |
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Unit |
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25 C |
85 C |
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125 C |
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VIH |
Minimum High±Level Input |
Vout = VCC ± 0.1 V |
2.0 |
1.5 |
1.5 |
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1.5 |
V |
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Voltage |
|Iout| v 20 μA |
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4.5 |
3.15 |
3.15 |
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3.15 |
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6.0 |
4.2 |
4.2 |
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4.2 |
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VIL |
Maximum Low±Level Input |
Vout = 0.1 V or VCC ± 0.1 V |
2.0 |
0.3 |
0.3 |
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0.3 |
V |
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Voltage |
|Iout| v 20 μA |
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4.5 |
0.9 |
0.9 |
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0.9 |
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6.0 |
1.2 |
1.2 |
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1.2 |
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VOH |
Minimum High±Level Output |
Vin = VIH |
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2.0 |
1.9 |
1.9 |
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1.9 |
V |
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Voltage |
|Iout| v 20 μA |
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4.5 |
4.4 |
4.4 |
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4.4 |
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6.0 |
5.9 |
5.9 |
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5.9 |
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Vin = VIH or VIL |
|Iout| v 4.0 mA |
4.5 |
3.98 |
3.84 |
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3.70 |
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|Iout| v 5.2 mA |
6.0 |
5.48 |
5.34 |
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5.20 |
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VOL |
Maximum Low±Level Output |
Vin = VIH or VIL |
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2.0 |
0.1 |
0.1 |
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0.1 |
V |
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Voltage |
|Iout| v 20 μA |
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4.5 |
0.1 |
0.1 |
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0.1 |
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6.0 |
0.1 |
0.1 |
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0.1 |
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Vin = VIH or VIL |
|Iout| v 4.0 mA |
4.5 |
0.26 |
0.33 |
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0.40 |
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|Iout| v 5.2 mA |
6.0 |
0.26 |
0.33 |
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0.40 |
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Iin |
Maximum Input Leakage Current |
Vin = VCC or GND |
6.0 |
± 0.1 |
± 1.0 |
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± 1.0 |
μA |
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Vin = 15 V |
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6.0 |
0.5 |
5.0 |
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5.0 |
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ICC |
Maximum Quiescent Supply |
Vin = 15 V or GND |
6.0 |
2 |
20 |
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40 |
μA |
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Current (per Package) |
Iout = 0 μA |
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High±Speed CMOS Data Book (DL129/D).
MOTOROLA |
2 |
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